From: Rob Herring <robh@kernel.org>
To: Yassine Oudjana <yassine.oudjana@gmail.com>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Tinghan Shen <tinghan.shen@mediatek.com>,
Ikjoon Jang <ikjn@chromium.org>,
Michael Turquette <mturquette@baylibre.com>,
Miles Chen <miles.chen@mediatek.com>,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Weiyi Lu <weiyi.lu@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Yassine Oudjana <y.oudjana@protonmail.com>,
Sam Shih <sam.shih@mediatek.com>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings
Date: Mon, 16 May 2022 18:48:26 -0500 [thread overview]
Message-ID: <20220516234826.GA3562658-robh@kernel.org> (raw)
In-Reply-To: <20220504122601.335495-2-y.oudjana@protonmail.com>
On Wed, 04 May 2022 16:25:50 +0400, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
>
> Add clock definitions for Mediatek MT6735 clocks provided by
> apmixedsys, topckgen, infracfg and pericfg.
>
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
> MAINTAINERS | 10 +++
> .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++
> .../clock/mediatek,mt6735-infracfg.h | 25 ++++++
> .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++
> .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++
> 5 files changed, 167 insertions(+)
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
>
Acked-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Yassine Oudjana <yassine.oudjana@gmail.com>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Tinghan Shen <tinghan.shen@mediatek.com>,
Ikjoon Jang <ikjn@chromium.org>,
Michael Turquette <mturquette@baylibre.com>,
Miles Chen <miles.chen@mediatek.com>,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Weiyi Lu <weiyi.lu@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Yassine Oudjana <y.oudjana@protonmail.com>,
Sam Shih <sam.shih@mediatek.com>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings
Date: Mon, 16 May 2022 18:48:26 -0500 [thread overview]
Message-ID: <20220516234826.GA3562658-robh@kernel.org> (raw)
In-Reply-To: <20220504122601.335495-2-y.oudjana@protonmail.com>
On Wed, 04 May 2022 16:25:50 +0400, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
>
> Add clock definitions for Mediatek MT6735 clocks provided by
> apmixedsys, topckgen, infracfg and pericfg.
>
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
> MAINTAINERS | 10 +++
> .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++
> .../clock/mediatek,mt6735-infracfg.h | 25 ++++++
> .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++
> .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++
> 5 files changed, 167 insertions(+)
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Yassine Oudjana <yassine.oudjana@gmail.com>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Tinghan Shen <tinghan.shen@mediatek.com>,
Ikjoon Jang <ikjn@chromium.org>,
Michael Turquette <mturquette@baylibre.com>,
Miles Chen <miles.chen@mediatek.com>,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Weiyi Lu <weiyi.lu@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Yassine Oudjana <y.oudjana@protonmail.com>,
Sam Shih <sam.shih@mediatek.com>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings
Date: Mon, 16 May 2022 18:48:26 -0500 [thread overview]
Message-ID: <20220516234826.GA3562658-robh@kernel.org> (raw)
In-Reply-To: <20220504122601.335495-2-y.oudjana@protonmail.com>
On Wed, 04 May 2022 16:25:50 +0400, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
>
> Add clock definitions for Mediatek MT6735 clocks provided by
> apmixedsys, topckgen, infracfg and pericfg.
>
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
> MAINTAINERS | 10 +++
> .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++
> .../clock/mediatek,mt6735-infracfg.h | 25 ++++++
> .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++
> .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++
> 5 files changed, 167 insertions(+)
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
> create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-16 23:48 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 12:25 [PATCH 00/13] Mediatek MT6735 main clock and reset drivers Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-16 23:48 ` Rob Herring [this message]
2022-05-16 23:48 ` Rob Herring
2022-05-16 23:48 ` Rob Herring
2022-05-04 12:25 ` [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-16 23:49 ` Rob Herring
2022-05-16 23:49 ` Rob Herring
2022-05-16 23:49 ` Rob Herring
2022-05-04 12:25 ` [PATCH 03/13] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 15:29 ` Rob Herring
2022-05-04 15:29 ` Rob Herring
2022-05-04 15:29 ` Rob Herring
2022-05-04 12:25 ` [PATCH 04/13] clk: composite: Export clk_unregister_composite Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 05/13] clk: mediatek: Export mtk_free_clk_data Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 06/13] clk: mediatek: Add driver for MT6735 apmixedsys Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 07/13] clk: mediatek: Add driver for MT6735 topckgen Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 08/13] clk: mediatek: gate: Export mtk_clk_register_gates_with_dev Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:46 ` Rex-BC Chen
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:55 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 10/13] clk: mediatek: reset: Return mtk_reset pointer on register Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 11/13] clk: mediatek: reset: Implement mtk_unregister_reset_controller() API Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
2022-05-04 12:26 ` Yassine Oudjana
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