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From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Yassine Oudjana <y.oudjana@protonmail.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	Chen-Yu Tsai <wenst@chromium.org>,
	Tinghan Shen <tinghan.shen@mediatek.com>,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@collabora.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
	Miles Chen <miles.chen@mediatek.com>,
	Sam Shih <sam.shih@mediatek.com>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols
Date: Wed, 04 May 2022 16:55:08 +0400	[thread overview]
Message-ID: <WVZCBR.JP1KZVF249S43@gmail.com> (raw)
In-Reply-To: <fda797664ad3cde1143838bdf63cc587459b2c2f.camel@mediatek.com>


On Wed, May 4 2022 at 20:46:22 +0800, Rex-BC Chen 
<rex-bc.chen@mediatek.com> wrote:
> On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote:
>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>>  Export mtk_register_reset_controller and
>>  mtk_register_reset_controller_set_clr to support building reset
>>  drivers as modules.
>> 
>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>  ---
>>   drivers/clk/mediatek/reset.c | 2 ++
>>   1 file changed, 2 insertions(+)
>> 
>>  diff --git a/drivers/clk/mediatek/reset.c
>>  b/drivers/clk/mediatek/reset.c
>>  index bcec4b89f449..6c2effe6afef 100644
>>  --- a/drivers/clk/mediatek/reset.c
>>  +++ b/drivers/clk/mediatek/reset.c
>>  @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller);
>> 
>>   void mtk_register_reset_controller_set_clr(struct device_node *np,
>>   	unsigned int num_regs, int regofs)
>>  @@ -136,5 +137,6 @@ void 
>> mtk_register_reset_controller_set_clr(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops_set_clr);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr);
>> 
>>   MODULE_LICENSE("GPL");
> 
> Hello Yassine,
> 
> Thanks for your patch for mediatek clk reset.
> But I have another series to cleanup mediatek clk reset drivers and
> most of my patches are reviewed.
> Please refer to
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849

Great! In that case I'll rebase my patches onto your series and see
if anything is missing.

Thanks,
Yassine



WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Yassine Oudjana <y.oudjana@protonmail.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	Chen-Yu Tsai <wenst@chromium.org>,
	Tinghan Shen <tinghan.shen@mediatek.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
	Miles Chen <miles.chen@mediatek.com>,
	Sam Shih <sam.shih@mediatek.com>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols
Date: Wed, 04 May 2022 16:55:08 +0400	[thread overview]
Message-ID: <WVZCBR.JP1KZVF249S43@gmail.com> (raw)
In-Reply-To: <fda797664ad3cde1143838bdf63cc587459b2c2f.camel@mediatek.com>


On Wed, May 4 2022 at 20:46:22 +0800, Rex-BC Chen 
<rex-bc.chen@mediatek.com> wrote:
> On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote:
>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>>  Export mtk_register_reset_controller and
>>  mtk_register_reset_controller_set_clr to support building reset
>>  drivers as modules.
>> 
>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>  ---
>>   drivers/clk/mediatek/reset.c | 2 ++
>>   1 file changed, 2 insertions(+)
>> 
>>  diff --git a/drivers/clk/mediatek/reset.c
>>  b/drivers/clk/mediatek/reset.c
>>  index bcec4b89f449..6c2effe6afef 100644
>>  --- a/drivers/clk/mediatek/reset.c
>>  +++ b/drivers/clk/mediatek/reset.c
>>  @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller);
>> 
>>   void mtk_register_reset_controller_set_clr(struct device_node *np,
>>   	unsigned int num_regs, int regofs)
>>  @@ -136,5 +137,6 @@ void 
>> mtk_register_reset_controller_set_clr(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops_set_clr);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr);
>> 
>>   MODULE_LICENSE("GPL");
> 
> Hello Yassine,
> 
> Thanks for your patch for mediatek clk reset.
> But I have another series to cleanup mediatek clk reset drivers and
> most of my patches are reviewed.
> Please refer to
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849

Great! In that case I'll rebase my patches onto your series and see
if anything is missing.

Thanks,
Yassine



_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <yassine.oudjana@gmail.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Yassine Oudjana <y.oudjana@protonmail.com>,
	Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	Chen-Yu Tsai <wenst@chromium.org>,
	Tinghan Shen <tinghan.shen@mediatek.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>, Ikjoon Jang <ikjn@chromium.org>,
	Miles Chen <miles.chen@mediatek.com>,
	Sam Shih <sam.shih@mediatek.com>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols
Date: Wed, 04 May 2022 16:55:08 +0400	[thread overview]
Message-ID: <WVZCBR.JP1KZVF249S43@gmail.com> (raw)
In-Reply-To: <fda797664ad3cde1143838bdf63cc587459b2c2f.camel@mediatek.com>


On Wed, May 4 2022 at 20:46:22 +0800, Rex-BC Chen 
<rex-bc.chen@mediatek.com> wrote:
> On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote:
>>  From: Yassine Oudjana <y.oudjana@protonmail.com>
>> 
>>  Export mtk_register_reset_controller and
>>  mtk_register_reset_controller_set_clr to support building reset
>>  drivers as modules.
>> 
>>  Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
>>  ---
>>   drivers/clk/mediatek/reset.c | 2 ++
>>   1 file changed, 2 insertions(+)
>> 
>>  diff --git a/drivers/clk/mediatek/reset.c
>>  b/drivers/clk/mediatek/reset.c
>>  index bcec4b89f449..6c2effe6afef 100644
>>  --- a/drivers/clk/mediatek/reset.c
>>  +++ b/drivers/clk/mediatek/reset.c
>>  @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller);
>> 
>>   void mtk_register_reset_controller_set_clr(struct device_node *np,
>>   	unsigned int num_regs, int regofs)
>>  @@ -136,5 +137,6 @@ void 
>> mtk_register_reset_controller_set_clr(struct
>>  device_node *np,
>>   	mtk_register_reset_controller_common(np, num_regs, regofs,
>>   		&mtk_reset_ops_set_clr);
>>   }
>>  +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr);
>> 
>>   MODULE_LICENSE("GPL");
> 
> Hello Yassine,
> 
> Thanks for your patch for mediatek clk reset.
> But I have another series to cleanup mediatek clk reset drivers and
> most of my patches are reviewed.
> Please refer to
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849

Great! In that case I'll rebase my patches onto your series and see
if anything is missing.

Thanks,
Yassine



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-05-04 12:57 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04 12:25 [PATCH 00/13] Mediatek MT6735 main clock and reset drivers Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-16 23:48   ` Rob Herring
2022-05-16 23:48     ` Rob Herring
2022-05-16 23:48     ` Rob Herring
2022-05-04 12:25 ` [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-16 23:49   ` Rob Herring
2022-05-16 23:49     ` Rob Herring
2022-05-16 23:49     ` Rob Herring
2022-05-04 12:25 ` [PATCH 03/13] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 15:29   ` Rob Herring
2022-05-04 15:29     ` Rob Herring
2022-05-04 15:29     ` Rob Herring
2022-05-04 12:25 ` [PATCH 04/13] clk: composite: Export clk_unregister_composite Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 05/13] clk: mediatek: Export mtk_free_clk_data Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 06/13] clk: mediatek: Add driver for MT6735 apmixedsys Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 07/13] clk: mediatek: Add driver for MT6735 topckgen Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 08/13] clk: mediatek: gate: Export mtk_clk_register_gates_with_dev Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:46   ` Rex-BC Chen
2022-05-04 12:46     ` Rex-BC Chen
2022-05-04 12:46     ` Rex-BC Chen
2022-05-04 12:55     ` Yassine Oudjana [this message]
2022-05-04 12:55       ` Yassine Oudjana
2022-05-04 12:55       ` Yassine Oudjana
2022-05-04 12:25 ` [PATCH 10/13] clk: mediatek: reset: Return mtk_reset pointer on register Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:25   ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 11/13] clk: mediatek: reset: Implement mtk_unregister_reset_controller() API Yassine Oudjana
2022-05-04 12:26   ` Yassine Oudjana
2022-05-04 12:26   ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Yassine Oudjana
2022-05-04 12:26   ` Yassine Oudjana
2022-05-04 12:26   ` Yassine Oudjana
2022-05-04 12:26 ` [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Yassine Oudjana
2022-05-04 12:26   ` Yassine Oudjana
2022-05-04 12:26   ` Yassine Oudjana

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