From: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de,
angelogioacchino.delregno@collabora.com,
chun-jie.chen@mediatek.com, wenst@chromium.org,
runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v7 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195
Date: Fri, 20 May 2022 11:30:34 -0400 [thread overview]
Message-ID: <20220520153034.v4dvh4bn2pon6nnr@notapiano> (raw)
In-Reply-To: <20220519125527.18544-17-rex-bc.chen@mediatek.com>
Hi Rex,
On Thu, May 19, 2022 at 08:55:24PM +0800, Rex-BC Chen wrote:
> We will use mediatek clock reset as infracfg_ao reset instead of
> ti-syscon. To support this, remove property of ti reset and add
> property of #reset-cells for mediatek clock reset.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b57e620c2c72..8e5ac11b19f1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,7 +10,6 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> -#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8195";
> @@ -295,17 +294,7 @@
> compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
I believe the 'simple-mfd' compatible was added only to make the
reset-controller subnode probe (at least this was the case for mt8192), so it
might make sense to drop it here as well.
Thanks,
Nícolas
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> -
> - infracfg_rst: reset-controller {
> - compatible = "ti,syscon-reset";
> - #reset-cells = <1>;
> - ti,reset-bits = <
> - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
> - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
> - >;
> - };
> + #reset-cells = <1>;
> };
>
> pericfg: syscon@10003000 {
> --
> 2.18.0
>
>
WARNING: multiple messages have this Message-ID (diff)
From: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de,
angelogioacchino.delregno@collabora.com,
chun-jie.chen@mediatek.com, wenst@chromium.org,
runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v7 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195
Date: Fri, 20 May 2022 11:30:34 -0400 [thread overview]
Message-ID: <20220520153034.v4dvh4bn2pon6nnr@notapiano> (raw)
In-Reply-To: <20220519125527.18544-17-rex-bc.chen@mediatek.com>
Hi Rex,
On Thu, May 19, 2022 at 08:55:24PM +0800, Rex-BC Chen wrote:
> We will use mediatek clock reset as infracfg_ao reset instead of
> ti-syscon. To support this, remove property of ti reset and add
> property of #reset-cells for mediatek clock reset.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b57e620c2c72..8e5ac11b19f1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,7 +10,6 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> -#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8195";
> @@ -295,17 +294,7 @@
> compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
I believe the 'simple-mfd' compatible was added only to make the
reset-controller subnode probe (at least this was the case for mt8192), so it
might make sense to drop it here as well.
Thanks,
Nícolas
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> -
> - infracfg_rst: reset-controller {
> - compatible = "ti,syscon-reset";
> - #reset-cells = <1>;
> - ti,reset-bits = <
> - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
> - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
> - >;
> - };
> + #reset-cells = <1>;
> };
>
> pericfg: syscon@10003000 {
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de,
angelogioacchino.delregno@collabora.com,
chun-jie.chen@mediatek.com, wenst@chromium.org,
runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v7 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195
Date: Fri, 20 May 2022 11:30:34 -0400 [thread overview]
Message-ID: <20220520153034.v4dvh4bn2pon6nnr@notapiano> (raw)
In-Reply-To: <20220519125527.18544-17-rex-bc.chen@mediatek.com>
Hi Rex,
On Thu, May 19, 2022 at 08:55:24PM +0800, Rex-BC Chen wrote:
> We will use mediatek clock reset as infracfg_ao reset instead of
> ti-syscon. To support this, remove property of ti reset and add
> property of #reset-cells for mediatek clock reset.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b57e620c2c72..8e5ac11b19f1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,7 +10,6 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> -#include <dt-bindings/reset/ti-syscon.h>
>
> / {
> compatible = "mediatek,mt8195";
> @@ -295,17 +294,7 @@
> compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
I believe the 'simple-mfd' compatible was added only to make the
reset-controller subnode probe (at least this was the case for mt8192), so it
might make sense to drop it here as well.
Thanks,
Nícolas
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> -
> - infracfg_rst: reset-controller {
> - compatible = "ti,syscon-reset";
> - #reset-cells = <1>;
> - ti,reset-bits = <
> - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
> - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
> - >;
> - };
> + #reset-cells = <1>;
> };
>
> pericfg: syscon@10003000 {
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-20 15:30 UTC|newest]
Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-19 12:55 [PATCH v7 00/19] Cleanup MediaTek clk reset drivers and support SoCs Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 01/19] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 02/19] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 03/19] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 04/19] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 14:55 ` Nícolas F. R. A. Prado
2022-05-20 14:55 ` Nícolas F. R. A. Prado
2022-05-20 14:55 ` Nícolas F. R. A. Prado
2022-05-23 5:08 ` Rex-BC Chen
2022-05-23 5:08 ` Rex-BC Chen
2022-05-23 5:08 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 05/19] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 15:12 ` Nícolas F. R. A. Prado
2022-05-20 15:12 ` Nícolas F. R. A. Prado
2022-05-20 15:12 ` Nícolas F. R. A. Prado
2022-05-23 5:09 ` Rex-BC Chen
2022-05-23 5:09 ` Rex-BC Chen
2022-05-23 5:09 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 06/19] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 15:18 ` Nícolas F. R. A. Prado
2022-05-20 15:18 ` Nícolas F. R. A. Prado
2022-05-20 15:18 ` Nícolas F. R. A. Prado
2022-05-23 5:10 ` Rex-BC Chen
2022-05-23 5:10 ` Rex-BC Chen
2022-05-23 5:10 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 08/19] clk: mediatek: reset: Support inuput argument index mode Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 09/19] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 10/19] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 11/19] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 12/19] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 13/19] dt-bindings: reset: mediatek: Add infra_ao reset index " Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 2:58 ` Rex-BC Chen
2022-05-20 2:58 ` Rex-BC Chen
2022-05-20 2:58 ` Rex-BC Chen
2022-05-20 3:10 ` Chen-Yu Tsai
2022-05-20 3:10 ` Chen-Yu Tsai
2022-05-20 3:10 ` Chen-Yu Tsai
[not found] ` <20220521042323.BA60AC385A5@smtp.kernel.org>
2022-05-23 5:14 ` Rex-BC Chen
2022-05-23 5:14 ` Rex-BC Chen
2022-05-23 5:14 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 14/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 15:30 ` Nícolas F. R. A. Prado [this message]
2022-05-20 15:30 ` Nícolas F. R. A. Prado
2022-05-20 15:30 ` Nícolas F. R. A. Prado
2022-05-23 5:11 ` Rex-BC Chen
2022-05-23 5:11 ` Rex-BC Chen
2022-05-23 5:11 ` Rex-BC Chen
2022-05-19 12:55 ` [PATCH v7 17/19] dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 22:32 ` Rob Herring
2022-05-20 22:32 ` Rob Herring
2022-05-20 22:32 ` Rob Herring
2022-05-19 12:55 ` [PATCH v7 18/19] dt-bindings: arm: mediatek: Add #reset-cells property " Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 22:33 ` Rob Herring
2022-05-20 22:33 ` Rob Herring
2022-05-20 22:33 ` Rob Herring
2022-05-19 12:55 ` [PATCH v7 19/19] clk: mediatek: reset: Add infra_ao reset support " Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-19 12:55 ` Rex-BC Chen
2022-05-20 15:40 ` [PATCH v7 00/19] Cleanup MediaTek clk reset drivers and support SoCs Nícolas F. R. A. Prado
2022-05-20 15:40 ` Nícolas F. R. A. Prado
2022-05-20 15:40 ` Nícolas F. R. A. Prado
2022-05-23 5:12 ` Rex-BC Chen
2022-05-23 5:12 ` Rex-BC Chen
2022-05-23 5:12 ` Rex-BC Chen
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