Re: [PATCH v7 00/19] Cleanup MediaTek clk reset drivers and support SoCs - Rex-BC Chen

From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
Cc: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <p.zabel@pengutronix.de>,
	<angelogioacchino.delregno@collabora.com>,
	<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
	<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [PATCH v7 00/19] Cleanup MediaTek clk reset drivers and support SoCs
Date: Mon, 23 May 2022 13:12:19 +0800	[thread overview]
Message-ID: <5484a9e2be7e71c3ecc86f4184f076be09ee9420.camel@mediatek.com> (raw)
In-Reply-To: <20220520154020.dywardvr3silhjwk@notapiano>

On Fri, 2022-05-20 at 11:40 -0400, Nícolas F. R. A. Prado wrote:
> On Thu, May 19, 2022 at 08:55:08PM +0800, Rex-BC Chen wrote:
> > In this series, we cleanup MediaTek clock reset drivers in
> > clk/mediatek
> > folder. MediaTek clock reset driver is used to provide reset
> > control
> > of modules controlled in clk, like infra_ao.
> > 
> > Changes for v7:
> > 1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1].
> > 2. Add support for MT8186.
> > 
> > [1]: 
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003__;!!CTRNKA9wMg0ARbw!3N_R1R2qXYd-vLUE-Bzrc1ZD_39liFO6Vz_RyJdPiuAyoMHO4TuaoOwWk1ka50bVe_0fdyJakB-FzCLGjzdVtsd6sQ$
> >  
> > 
> > Changes for v6:
> > 1. Add a new patch to support inuput argument index mode.
> > 2. Revise definition in reset.h to index.
> > 
> > Rex-BC Chen (19):
> >   clk: mediatek: reset: Add reset.h
> >   clk: mediatek: reset: Fix written reset bit offset
> >   clk: mediatek: reset: Refine and reorder functions in reset.c
> >   clk: mediatek: reset: Extract common drivers to update function
> >   clk: mediatek: reset: Merge and revise reset register function
> >   clk: mediatek: reset: Revise structure to control reset register
> >   clk: mediatek: reset: Support nonsequence base offsets of reset
> >     registers
> >   clk: mediatek: reset: Support inuput argument index mode
> >   clk: mediatek: reset: Change return type for clock reset register
> >     function
> >   clk: mediatek: reset: Add new register reset function with device
> >   clk: mediatek: reset: Add reset support for simple probe
> >   dt-bindings: arm: mediatek: Add #reset-cells property for
> >     MT8192/MT8195
> >   dt-bindings: reset: mediatek: Add infra_ao reset index for
> >     MT8192/MT8195
> >   clk: mediatek: reset: Add infra_ao reset support for
> > MT8192/MT8195
> >   arm64: dts: mediatek: Add infra #reset-cells property for MT8192
> >   arm64: dts: mediatek: Add infra #reset-cells property for MT8195
> >   dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
> >   dt-bindings: arm: mediatek: Add #reset-cells property for MT8186
> >   clk: mediatek: reset: Add infra_ao reset support for MT8186
> 
> For the whole series:
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> And also
> 
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> on mt8192-asurada-spherion. PCIe resets work as intended by adding on
> the pcie
> node 
> 
> +                       resets = <&infracfg
> MT8192_INFRA_RST2_PEXTP_PHY_SWRST>,
> +                                <&infracfg
> MT8192_INFRA_RST4_PCIE_TOP_SWRST>;
> +                       reset-names = "phy", "mac";
> 
> Thanks for the great work on this series, Rex!
> 
> Nícolas

Hello Nícolas,

Thanks for helping me to test this series in MT8192.

BRs,
Rex