From: Tinghan Shen <tinghan.shen@mediatek.com>
To: Bjorn Andersson <bjorn.andersson@linaro.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Lee Jones <lee.jones@linaro.org>,
Benson Leung <bleung@chromium.org>,
"Guenter Roeck" <groeck@chromium.org>,
Sebastian Reichel <sebastian.reichel@collabora.com>,
Daisuke Nojiri <dnojiri@chromium.org>,
Kees Cook <keescook@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
Prashant Malani <pmalani@chromium.org>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <chrome-platform@lists.linux.dev>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<weishunc@google.com>
Subject: [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions
Date: Wed, 8 Jun 2022 16:35:47 +0800 [thread overview]
Message-ID: <20220608083553.8697-4-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com>
Add MT8195 SCP core 1 related register definitions.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index 73e8adf00de3..5582f4207fbf 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -47,6 +47,7 @@
#define MT8192_SCP2SPM_IPC_CLR 0x4094
#define MT8192_GIPC_IN_SET 0x4098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
+#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
#define MT8192_CORE0_SW_RSTN_SET 0x10004
@@ -60,6 +61,26 @@
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
+#define MT8195_CPU1_SRAM_PD 0x1084
+#define MT8195_SSHUB2APMCU_IPC_SET 0x4088
+#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C
+#define MT8195_CORE1_SW_RSTN_CLR 0x20000
+#define MT8195_CORE1_SW_RSTN_SET 0x20004
+#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
+#define MT8195_CORE1_WDT_IRQ 0x20030
+#define MT8195_CORE1_WDT_CFG 0x20034
+
+#define MT8195_SEC_CTRL 0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
+#define MT8195_L2TCM_OFFSET 0x850d0
+#define SCP_SRAM_REMAP_LOW 0
+#define SCP_SRAM_REMAP_HIGH 1
+#define SCP_SRAM_REMAP_OFFSET 2
+#define SCP_SRAM_REMAP_SIZE 3
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: Bjorn Andersson <bjorn.andersson@linaro.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Lee Jones <lee.jones@linaro.org>,
Benson Leung <bleung@chromium.org>,
Guenter Roeck <groeck@chromium.org>,
Sebastian Reichel <sebastian.reichel@collabora.com>,
Daisuke Nojiri <dnojiri@chromium.org>,
Kees Cook <keescook@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
Prashant Malani <pmalani@chromium.org>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <chrome-platform@lists.linux.dev>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<weishunc@google.com>
Subject: [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions
Date: Wed, 8 Jun 2022 16:35:47 +0800 [thread overview]
Message-ID: <20220608083553.8697-4-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com>
Add MT8195 SCP core 1 related register definitions.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index 73e8adf00de3..5582f4207fbf 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -47,6 +47,7 @@
#define MT8192_SCP2SPM_IPC_CLR 0x4094
#define MT8192_GIPC_IN_SET 0x4098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
+#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
#define MT8192_CORE0_SW_RSTN_SET 0x10004
@@ -60,6 +61,26 @@
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
+#define MT8195_CPU1_SRAM_PD 0x1084
+#define MT8195_SSHUB2APMCU_IPC_SET 0x4088
+#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C
+#define MT8195_CORE1_SW_RSTN_CLR 0x20000
+#define MT8195_CORE1_SW_RSTN_SET 0x20004
+#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
+#define MT8195_CORE1_WDT_IRQ 0x20030
+#define MT8195_CORE1_WDT_CFG 0x20034
+
+#define MT8195_SEC_CTRL 0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
+#define MT8195_L2TCM_OFFSET 0x850d0
+#define SCP_SRAM_REMAP_LOW 0
+#define SCP_SRAM_REMAP_HIGH 1
+#define SCP_SRAM_REMAP_OFFSET 2
+#define SCP_SRAM_REMAP_SIZE 3
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Tinghan Shen <tinghan.shen@mediatek.com>
To: Bjorn Andersson <bjorn.andersson@linaro.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Lee Jones <lee.jones@linaro.org>,
Benson Leung <bleung@chromium.org>,
Guenter Roeck <groeck@chromium.org>,
Sebastian Reichel <sebastian.reichel@collabora.com>,
Daisuke Nojiri <dnojiri@chromium.org>,
Kees Cook <keescook@chromium.org>,
Tinghan Shen <tinghan.shen@mediatek.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
Prashant Malani <pmalani@chromium.org>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <chrome-platform@lists.linux.dev>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<weishunc@google.com>
Subject: [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions
Date: Wed, 8 Jun 2022 16:35:47 +0800 [thread overview]
Message-ID: <20220608083553.8697-4-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com>
Add MT8195 SCP core 1 related register definitions.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index 73e8adf00de3..5582f4207fbf 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -47,6 +47,7 @@
#define MT8192_SCP2SPM_IPC_CLR 0x4094
#define MT8192_GIPC_IN_SET 0x4098
#define MT8192_HOST_IPC_INT_BIT BIT(0)
+#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)
#define MT8192_CORE0_SW_RSTN_CLR 0x10000
#define MT8192_CORE0_SW_RSTN_SET 0x10004
@@ -60,6 +61,26 @@
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
+#define MT8195_CPU1_SRAM_PD 0x1084
+#define MT8195_SSHUB2APMCU_IPC_SET 0x4088
+#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C
+#define MT8195_CORE1_SW_RSTN_CLR 0x20000
+#define MT8195_CORE1_SW_RSTN_SET 0x20004
+#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
+#define MT8195_CORE1_WDT_IRQ 0x20030
+#define MT8195_CORE1_WDT_CFG 0x20034
+
+#define MT8195_SEC_CTRL 0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
+#define MT8195_L2TCM_OFFSET 0x850d0
+#define SCP_SRAM_REMAP_LOW 0
+#define SCP_SRAM_REMAP_HIGH 1
+#define SCP_SRAM_REMAP_OFFSET 2
+#define SCP_SRAM_REMAP_SIZE 3
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-06-08 8:36 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-08 8:35 [PATCH v2 0/9] Add support for MT8195 SCP 2nd core Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` [PATCH v2 1/9] dt-binding: remoteproc: mediatek: Support dual-core SCP Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-09 20:51 ` Rob Herring
2022-06-09 20:51 ` Rob Herring
2022-06-09 20:51 ` Rob Herring
2022-06-08 8:35 ` [PATCH v2 2/9] remoteproc: mediatek: Support hanlding scp core 1 wdt timeout Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-08-29 17:40 ` Mathieu Poirier
2022-08-29 17:40 ` Mathieu Poirier
2022-09-08 10:38 ` Tinghan Shen
2022-09-08 10:38 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen [this message]
2022-06-08 8:35 ` [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-08-29 17:46 ` Mathieu Poirier
2022-08-29 17:46 ` Mathieu Poirier
2022-06-08 8:35 ` [PATCH v2 4/9] remoteproc: mediatek: Support probing for the 2nd core of dual-core SCP Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-08-29 19:42 ` Mathieu Poirier
2022-08-29 19:42 ` Mathieu Poirier
2022-09-08 11:17 ` Tinghan Shen
2022-09-08 11:17 ` Tinghan Shen
[not found] ` <CANLsYkx6kXk8u_ajFbnhdWTkZBLtrq_z02jryLBSVH0x--_ZFw@mail.gmail.com>
2022-09-16 11:59 ` TingHan Shen
2022-09-16 11:59 ` TingHan Shen
2022-09-16 17:15 ` Mathieu Poirier
2022-09-16 17:15 ` Mathieu Poirier
2022-09-19 9:46 ` TingHan Shen
2022-09-19 9:46 ` TingHan Shen
2022-09-19 20:53 ` Mathieu Poirier
2022-09-19 20:53 ` Mathieu Poirier
2022-09-23 7:12 ` Peng Fan
2022-09-23 7:12 ` Peng Fan
2022-06-08 8:35 ` [PATCH v2 5/9] remoteproc: mediatek: Add chip dependent operations for SCP core 1 Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` [PATCH v2 6/9] remoteproc: mediatek: Add SCP core 1 SRAM offset Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` [PATCH v2 7/9] remoteproc: mediatek: Add SCP core 1 as a rproc subdevice Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` [PATCH v2 8/9] remoteproc: mediatek: Wait SCP core 1 probe done Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` [PATCH v2 9/9] mfd: cros_ec: Add SCP core 1 as a new CrOS EC MCU Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-08 8:35 ` Tinghan Shen
2022-06-09 5:45 ` [PATCH v2 0/9] Add support for MT8195 SCP 2nd core Tinghan Shen
2022-06-09 5:45 ` Tinghan Shen
2022-06-09 5:45 ` Tinghan Shen
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