From: Samuel Holland <samuel@sholland.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Marc Zyngier <maz@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Cc: Guo Ren <guoren@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Geert Uytterhoeven <geert+renesas@glider.be>, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Samuel Holland <samuel@sholland.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Date: Thu, 30 Jun 2022 05:02:37 -0500 [thread overview] Message-ID: <20220630100241.35233-1-samuel@sholland.org> (raw) This patch series adds PLIC support for Renesas RZ/Five SoC. Since the T-HEAD C900 PLIC has the same behavior, it also applies the fix for that variant. This series is an update of v2 of the RZ/Five series[0], and replaces the separate T-HEAD series[1]. [0]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [1]: https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/ Changes in v3: - Add a more detailed explanation for why #interrupt-cells differs - Add andestech,nceplic100 as a fallback compatible - Separate the conditional part of the binding into two blocks (one for the PLIC implementation and the other for the SoC integration) - Use a quirk bit for selecting the flow instead of a variant ID - Use the andestech,nceplic100 compatible to select the new behavior - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack always gets called - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL - Use the same name for plic_edge_chip as plic_chip Changes in v2: - Fixed review comments pointed by Marc and Krzysztof. Changes in v1: - Fixed review comments pointed by Rob and Geert. - Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC. Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Samuel Holland (2): dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling .../sifive,plic-1.0.0.yaml | 65 +++++++++++++-- drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++-- 2 files changed, 135 insertions(+), 10 deletions(-) -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Marc Zyngier <maz@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Cc: Guo Ren <guoren@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Geert Uytterhoeven <geert+renesas@glider.be>, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Samuel Holland <samuel@sholland.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Date: Thu, 30 Jun 2022 05:02:37 -0500 [thread overview] Message-ID: <20220630100241.35233-1-samuel@sholland.org> (raw) This patch series adds PLIC support for Renesas RZ/Five SoC. Since the T-HEAD C900 PLIC has the same behavior, it also applies the fix for that variant. This series is an update of v2 of the RZ/Five series[0], and replaces the separate T-HEAD series[1]. [0]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [1]: https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/ Changes in v3: - Add a more detailed explanation for why #interrupt-cells differs - Add andestech,nceplic100 as a fallback compatible - Separate the conditional part of the binding into two blocks (one for the PLIC implementation and the other for the SoC integration) - Use a quirk bit for selecting the flow instead of a variant ID - Use the andestech,nceplic100 compatible to select the new behavior - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack always gets called - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL - Use the same name for plic_edge_chip as plic_chip Changes in v2: - Fixed review comments pointed by Marc and Krzysztof. Changes in v1: - Fixed review comments pointed by Rob and Geert. - Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC. Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Samuel Holland (2): dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling .../sifive,plic-1.0.0.yaml | 65 +++++++++++++-- drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++-- 2 files changed, 135 insertions(+), 10 deletions(-) -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-06-30 10:02 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-30 10:02 Samuel Holland [this message] 2022-06-30 10:02 ` [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Samuel Holland 2022-06-30 10:02 ` [PATCH v3 1/4] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Lad Prabhakar 2022-06-30 10:02 ` [PATCH v3 2/4] irqchip/sifive-plic: Add support for " Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Lad Prabhakar 2022-06-30 10:02 ` [PATCH v3 3/4] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Samuel Holland 2022-06-30 10:02 ` [PATCH v3 4/4] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-06-30 23:43 ` Guo Ren 2022-06-30 23:43 ` Guo Ren 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Samuel Holland 2022-07-01 14:28 ` [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Marc Zyngier 2022-07-01 14:28 ` Marc Zyngier 2022-07-13 3:19 ` Palmer Dabbelt 2022-07-13 3:19 ` Palmer Dabbelt 2022-07-13 7:00 ` Conor.Dooley 2022-07-13 7:00 ` Conor.Dooley
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