From: Samuel Holland <samuel@sholland.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Marc Zyngier <maz@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Cc: Guo Ren <guoren@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Geert Uytterhoeven <geert+renesas@glider.be>, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Samuel Holland <samuel@sholland.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/4] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Date: Thu, 30 Jun 2022 05:02:40 -0500 [thread overview] Message-ID: <20220630100241.35233-4-samuel@sholland.org> (raw) In-Reply-To: <20220630100241.35233-1-samuel@sholland.org> The RISC-V PLIC specification unfortunately allows PLIC implementations to ignore edges seen while an edge-triggered interrupt is being handled: Depending on the design of the device and the interrupt handler, in between sending an interrupt request and receiving notice of its handler’s completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus it also needs to inform software about each interrupt's trigger type, so the driver can use the right interrupt flow. Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Samuel Holland <samuel@sholland.org> --- Changes in v3: - Rebased on top of the RZ/Five patches .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index cd2b8bcaec3b..92e0f8c3eff2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -33,7 +33,7 @@ description: it is not included in the interrupt specifier. In the second case, software needs to know the trigger type, so it can reorder the interrupt flow to avoid missing interrupts. This special handling is needed by at least the Renesas - RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100). + RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -112,6 +112,7 @@ allOf: contains: enum: - andestech,nceplic100 + - thead,c900-plic then: properties: -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Marc Zyngier <maz@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Cc: Guo Ren <guoren@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Geert Uytterhoeven <geert+renesas@glider.be>, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Samuel Holland <samuel@sholland.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/4] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Date: Thu, 30 Jun 2022 05:02:40 -0500 [thread overview] Message-ID: <20220630100241.35233-4-samuel@sholland.org> (raw) In-Reply-To: <20220630100241.35233-1-samuel@sholland.org> The RISC-V PLIC specification unfortunately allows PLIC implementations to ignore edges seen while an edge-triggered interrupt is being handled: Depending on the design of the device and the interrupt handler, in between sending an interrupt request and receiving notice of its handler’s completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus it also needs to inform software about each interrupt's trigger type, so the driver can use the right interrupt flow. Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Samuel Holland <samuel@sholland.org> --- Changes in v3: - Rebased on top of the RZ/Five patches .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index cd2b8bcaec3b..92e0f8c3eff2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -33,7 +33,7 @@ description: it is not included in the interrupt specifier. In the second case, software needs to know the trigger type, so it can reorder the interrupt flow to avoid missing interrupts. This special handling is needed by at least the Renesas - RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100). + RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC. While the RISC-V ISA doesn't specify a memory layout for the PLIC, the "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that @@ -112,6 +112,7 @@ allOf: contains: enum: - andestech,nceplic100 + - thead,c900-plic then: properties: -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-06-30 10:03 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-30 10:02 [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-06-30 10:02 ` [PATCH v3 1/4] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Lad Prabhakar 2022-06-30 10:02 ` [PATCH v3 2/4] irqchip/sifive-plic: Add support for " Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Lad Prabhakar 2022-06-30 10:02 ` Samuel Holland [this message] 2022-06-30 10:02 ` [PATCH v3 3/4] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Samuel Holland 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Samuel Holland 2022-06-30 10:02 ` [PATCH v3 4/4] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Samuel Holland 2022-06-30 10:02 ` Samuel Holland 2022-06-30 23:43 ` Guo Ren 2022-06-30 23:43 ` Guo Ren 2022-07-01 14:37 ` [irqchip: irq/irqchip-next] " irqchip-bot for Samuel Holland 2022-07-01 14:28 ` [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Marc Zyngier 2022-07-01 14:28 ` Marc Zyngier 2022-07-13 3:19 ` Palmer Dabbelt 2022-07-13 3:19 ` Palmer Dabbelt 2022-07-13 7:00 ` Conor.Dooley 2022-07-13 7:00 ` Conor.Dooley
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