From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Joey Gouly <joey.gouly@arm.com>,
linux-arm-kernel@lists.infradead.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v7 18/28] arm64/sysreg: Convert DCZID_EL0 to automatic generation
Date: Mon, 4 Jul 2022 18:02:52 +0100 [thread overview]
Message-ID: <20220704170302.2609529-19-broonie@kernel.org> (raw)
In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org>
Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 5 -----
arch/arm64/tools/sysreg | 6 ++++++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 234f9a3844de..1a6a04b96dfa 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,8 +461,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
-
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
@@ -1081,9 +1079,6 @@
#define MVFR2_FPMISC_SHIFT 4
#define MVFR2_SIMDMISC_SHIFT 0
-#define DCZID_EL0_DZP_SHIFT 4
-#define DCZID_EL0_BS_SHIFT 0
-
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a9f4c157c4be..c286b62958ea 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -294,6 +294,12 @@ Res0 13:4
Field 3:0 IminLine
EndSysreg
+Sysreg DCZID_EL0 3 3 0 0 7
+Res0 63:5
+Field 4 DZP
+Field 3:0 BS
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
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next prev parent reply other threads:[~2022-07-04 17:12 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-04 17:02 [PATCH v7 00/28] arm64/sysreg: More system register generation Mark Brown
2022-07-04 17:02 ` [PATCH v7 01/28] arm64/cpuinfo: Remove references to reserved cache type Mark Brown
2022-07-04 17:02 ` [PATCH v7 02/28] arm64/idreg: Fix tab/space damage Mark Brown
2022-07-04 17:02 ` [PATCH v7 03/28] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
2022-07-04 17:02 ` [PATCH v7 04/28] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-07-04 17:02 ` [PATCH v7 05/28] arm64/cache: Restrict which headers are included in __ASSEMBLY__ Mark Brown
2022-07-04 17:02 ` [PATCH v7 06/28] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-07-04 17:02 ` [PATCH v7 07/28] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-07-04 17:02 ` [PATCH v7 08/28] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-07-04 17:02 ` [PATCH v7 09/28] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
2022-07-04 17:02 ` [PATCH v7 10/28] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-07-04 17:02 ` [PATCH v7 11/28] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-07-04 17:02 ` [PATCH v7 12/28] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-07-04 17:02 ` [PATCH v7 13/28] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-07-04 17:02 ` [PATCH v7 14/28] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-07-04 17:02 ` [PATCH v7 15/28] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-07-04 17:02 ` [PATCH v7 16/28] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 17/28] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-07-04 17:02 ` Mark Brown [this message]
2022-07-04 17:02 ` [PATCH v7 19/28] arm64/sysreg: Convert GMID " Mark Brown
2022-07-04 17:02 ` [PATCH v7 20/28] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 21/28] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 22/28] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 23/28] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 24/28] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-07-04 17:02 ` [PATCH v7 25/28] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-07-04 17:03 ` [PATCH v7 26/28] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-07-04 17:03 ` [PATCH v7 27/28] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-07-04 17:03 ` [PATCH v7 28/28] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown
2022-07-05 13:31 ` [PATCH v7 00/28] arm64/sysreg: More system register generation Will Deacon
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