From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Will Deacon <will@kernel.org> Subject: [v3 1/5] RISC-V: Fix counter restart during overflow for RV32 Date: Mon, 11 Jul 2022 10:46:28 -0700 [thread overview] Message-ID: <20220711174632.4186047-2-atishp@rivosinc.com> (raw) In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> Pass the upper half of the initial value of the counter correctly for RV32. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Signed-off-by: Atish Patra <atishp@rivosinc.com> --- drivers/perf/riscv_pmu_sbi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index dca3537a8dcc..0cb694b794ae 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, hwc = &event->hw; max_period = riscv_pmu_ctr_get_width_mask(event); init_val = local64_read(&hwc->prev_count) & max_period; +#if defined(CONFIG_32BIT) + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, init_val >> 32, 0); +#else sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); +#endif } ctr_ovf_mask = ctr_ovf_mask >> 1; idx++; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Will Deacon <will@kernel.org> Subject: [v3 1/5] RISC-V: Fix counter restart during overflow for RV32 Date: Mon, 11 Jul 2022 10:46:28 -0700 [thread overview] Message-ID: <20220711174632.4186047-2-atishp@rivosinc.com> (raw) In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com> Pass the upper half of the initial value of the counter correctly for RV32. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Signed-off-by: Atish Patra <atishp@rivosinc.com> --- drivers/perf/riscv_pmu_sbi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index dca3537a8dcc..0cb694b794ae 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, hwc = &event->hw; max_period = riscv_pmu_ctr_get_width_mask(event); init_val = local64_read(&hwc->prev_count) & max_period; +#if defined(CONFIG_32BIT) + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, init_val >> 32, 0); +#else sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); +#endif } ctr_ovf_mask = ctr_ovf_mask >> 1; idx++; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-07-11 17:46 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-11 17:46 [v3 0/5] Miscallenous improvement & fixes for the PMU driver Atish Patra 2022-07-11 17:46 ` Atish Patra 2022-07-11 17:46 ` Atish Patra [this message] 2022-07-11 17:46 ` [v3 1/5] RISC-V: Fix counter restart during overflow for RV32 Atish Patra 2022-07-12 1:45 ` Guo Ren 2022-07-12 1:45 ` Guo Ren 2022-07-11 17:46 ` [v3 2/5] RISC-V: Update user page mapping only once during start Atish Patra 2022-07-11 17:46 ` Atish Patra 2022-07-12 1:54 ` Guo Ren 2022-07-12 1:54 ` Guo Ren 2022-07-13 0:59 ` Atish Patra 2022-07-13 0:59 ` Atish Patra 2022-07-11 17:46 ` [v3 3/5] RISC-V: Fix SBI PMU calls for RV32 Atish Patra 2022-07-11 17:46 ` Atish Patra 2022-07-11 17:46 ` [v3 4/5] RISC-V: Move counter info definition to sbi header file Atish Patra 2022-07-11 17:46 ` Atish Patra 2022-07-11 17:46 ` [v3 5/5] RISC-V: Improve SBI definitions Atish Patra 2022-07-11 17:46 ` Atish Patra 2022-08-12 2:32 ` [v3 0/5] Miscallenous improvement & fixes for the PMU driver Palmer Dabbelt 2022-08-12 2:32 ` Palmer Dabbelt
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