Re: [v3 0/5] Miscallenous improvement & fixes for the PMU driver

From: Palmer Dabbelt <palmer@dabbelt.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org, Atish Patra <atishp@rivosinc.com>,
	aou@eecs.berkeley.edu, anup@brainfault.org,
	atishp@atishpatra.org, guoren@kernel.org,
	linux-riscv@lists.infradead.org, mark.rutland@arm.com,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Will Deacon <will@kernel.org>
Subject: Re: [v3  0/5] Miscallenous improvement & fixes for the PMU driver
Date: Thu, 11 Aug 2022 19:32:03 -0700 (PDT)	[thread overview]
Message-ID: <mhng-a68b84d8-d7c4-4048-b64e-0a5c7403fdd9@palmer-ri-x1c9> (raw)
In-Reply-To: <20220711174632.4186047-1-atishp@rivosinc.com>

On Mon, 11 Jul 2022 10:46:27 PDT (-0700), Atish Patra wrote:
> This series fixes issues PMU driver code.
> PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
> user page update issue during counter start.
>
> PATCH 4 & 5 improves the SBI PMU definition.
>
> Changes from v2->v3:
> 1. Added two more patches that fixes few typos and enable support
> for perf support in KVM.
>
> Changes from v1->v2:
> 1. Add proper compile time rv32 checks.
>
> Atish Patra (5):
> RISC-V: Fix counter restart during overflow for RV32
> RISC-V: Update user page mapping only once during start
> RISC-V: Fix SBI PMU calls for RV32
> RISC-V: Move counter info definition to sbi header file
> RISC-V: Improve SBI definitions
>
> arch/riscv/include/asm/sbi.h | 32 ++++++++++++++++++++++++++++++--
> drivers/perf/riscv_pmu.c     |  1 -
> drivers/perf/riscv_pmu_sbi.c | 30 ++++++++++++++++--------------
> 3 files changed, 46 insertions(+), 17 deletions(-)

Sorry, I guess I'd forgotten that Will asked me to merge this one.  
Thanks to Atish for reminding me, this is on for-next.