From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 12/14] drm/i915/xelpmp: Expose media as another GT Date: Tue, 6 Sep 2022 16:49:32 -0700 [thread overview] Message-ID: <20220906234934.3655440-13-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220906234934.3655440-1-matthew.d.roper@intel.com> Xe_LPM+ platforms have "standalone media." I.e., the media unit is designed as an additional GT with its own engine list, GuC, forcewake, etc. Let's allow platforms to include media GTs in their device info. v2: - Simplify GSI register handling and split it out to a separate patch for ease of review. (Daniele) Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 ++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +++++++++ drivers/gpu/drm/i915/i915_pci.c | 14 +++++++++ 7 files changed, 84 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 522ef9b4aff3..e83e4cd46968 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -123,6 +123,7 @@ gt-y += \ gt/intel_ring.o \ gt/intel_ring_submission.o \ gt/intel_rps.o \ + gt/intel_sa_media.o \ gt/intel_sseu.o \ gt/intel_sseu_debugfs.o \ gt/intel_timeline.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index aa0e40987798..9b9c0ea73b7f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -31,6 +31,7 @@ #include "intel_rc6.h" #include "intel_renderstate.h" #include "intel_rps.h" +#include "intel_sa_media.h" #include "intel_gt_sysfs.h" #include "intel_uncore.h" #include "shmem_utils.h" @@ -864,6 +865,11 @@ int intel_gt_probe_all(struct drm_i915_private *i915) ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base); break; + case GT_MEDIA: + ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base, + gtdef->gsi_offset); + break; + case GT_PRIMARY: /* Primary GT should not appear in extra GT list */ default: diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index d414785003cc..fb2c56777480 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1578,4 +1578,12 @@ #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) +/* + * Standalone Media's non-engine GT registers are located at their regular GT + * offsets plus 0x380000. This extra offset is stored inside the intel_uncore + * structure so that the existing code can be used for both GTs without + * modification. + */ +#define MTL_MEDIA_GSI_BASE 0x380000 + #endif /* __INTEL_GT_REGS__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 82dc28643572..726695936a79 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -84,6 +84,7 @@ struct gt_defaults { enum intel_gt_type { GT_PRIMARY, GT_TILE, + GT_MEDIA, }; struct intel_gt { diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c new file mode 100644 index 000000000000..8c5c519457cc --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include <drm/drm_managed.h> + +#include "i915_drv.h" +#include "gt/intel_gt.h" +#include "gt/intel_sa_media.h" + +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, + u32 gsi_offset) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore; + + uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL); + if (!uncore) + return -ENOMEM; + + uncore->gsi_offset = gsi_offset; + + intel_gt_common_init_early(gt); + intel_uncore_init_early(uncore, gt); + + /* + * Standalone media shares the general MMIO space with the primary + * GT. We'll re-use the primary GT's mapping. + */ + uncore->regs = i915->uncore.regs; + if (drm_WARN_ON(&i915->drm, uncore->regs == NULL)) + return -EIO; + + gt->uncore = uncore; + gt->phys_addr = phys_addr; + + return 0; +} diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h b/drivers/gpu/drm/i915/gt/intel_sa_media.h new file mode 100644 index 000000000000..3afb310de932 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ +#ifndef __INTEL_SA_MEDIA__ +#define __INTEL_SA_MEDIA__ + +#include <linux/types.h> + +struct intel_gt; + +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, + u32 gsi_offset); + +#endif /* __INTEL_SA_MEDIA_H__ */ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 26b25d9434d6..19fc00bcd7b9 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -26,6 +26,9 @@ #include <drm/drm_drv.h> #include <drm/i915_pciids.h> +#include "gt/intel_gt_regs.h" +#include "gt/intel_sa_media.h" + #include "i915_driver.h" #include "i915_drv.h" #include "i915_pci.h" @@ -1115,6 +1118,16 @@ static const struct intel_device_info pvc_info = { .display.has_cdclk_crawl = 1, \ .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) +static const struct intel_gt_definition xelpmp_extra_gt[] = { + { + .type = GT_MEDIA, + .name = "Standalone Media GT", + .gsi_offset = MTL_MEDIA_GSI_BASE, + .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2), + }, + {} +}; + __maybe_unused static const struct intel_device_info mtl_info = { XE_HP_FEATURES, @@ -1128,6 +1141,7 @@ static const struct intel_device_info mtl_info = { .media.ver = 13, PLATFORM(INTEL_METEORLAKE), .display.has_modular_fia = 1, + .extra_gt_list = xelpmp_extra_gt, .has_flat_ccs = 0, .has_snoop = 1, .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Aravind Iddamsetty <aravind.iddamsetty@intel.com>, dri-devel@lists.freedesktop.org Subject: [PATCH v3 12/14] drm/i915/xelpmp: Expose media as another GT Date: Tue, 6 Sep 2022 16:49:32 -0700 [thread overview] Message-ID: <20220906234934.3655440-13-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220906234934.3655440-1-matthew.d.roper@intel.com> Xe_LPM+ platforms have "standalone media." I.e., the media unit is designed as an additional GT with its own engine list, GuC, forcewake, etc. Let's allow platforms to include media GTs in their device info. v2: - Simplify GSI register handling and split it out to a separate patch for ease of review. (Daniele) Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 ++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +++++++++ drivers/gpu/drm/i915/i915_pci.c | 14 +++++++++ 7 files changed, 84 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 522ef9b4aff3..e83e4cd46968 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -123,6 +123,7 @@ gt-y += \ gt/intel_ring.o \ gt/intel_ring_submission.o \ gt/intel_rps.o \ + gt/intel_sa_media.o \ gt/intel_sseu.o \ gt/intel_sseu_debugfs.o \ gt/intel_timeline.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index aa0e40987798..9b9c0ea73b7f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -31,6 +31,7 @@ #include "intel_rc6.h" #include "intel_renderstate.h" #include "intel_rps.h" +#include "intel_sa_media.h" #include "intel_gt_sysfs.h" #include "intel_uncore.h" #include "shmem_utils.h" @@ -864,6 +865,11 @@ int intel_gt_probe_all(struct drm_i915_private *i915) ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base); break; + case GT_MEDIA: + ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base, + gtdef->gsi_offset); + break; + case GT_PRIMARY: /* Primary GT should not appear in extra GT list */ default: diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index d414785003cc..fb2c56777480 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1578,4 +1578,12 @@ #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) +/* + * Standalone Media's non-engine GT registers are located at their regular GT + * offsets plus 0x380000. This extra offset is stored inside the intel_uncore + * structure so that the existing code can be used for both GTs without + * modification. + */ +#define MTL_MEDIA_GSI_BASE 0x380000 + #endif /* __INTEL_GT_REGS__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 82dc28643572..726695936a79 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -84,6 +84,7 @@ struct gt_defaults { enum intel_gt_type { GT_PRIMARY, GT_TILE, + GT_MEDIA, }; struct intel_gt { diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c new file mode 100644 index 000000000000..8c5c519457cc --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include <drm/drm_managed.h> + +#include "i915_drv.h" +#include "gt/intel_gt.h" +#include "gt/intel_sa_media.h" + +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, + u32 gsi_offset) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore; + + uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL); + if (!uncore) + return -ENOMEM; + + uncore->gsi_offset = gsi_offset; + + intel_gt_common_init_early(gt); + intel_uncore_init_early(uncore, gt); + + /* + * Standalone media shares the general MMIO space with the primary + * GT. We'll re-use the primary GT's mapping. + */ + uncore->regs = i915->uncore.regs; + if (drm_WARN_ON(&i915->drm, uncore->regs == NULL)) + return -EIO; + + gt->uncore = uncore; + gt->phys_addr = phys_addr; + + return 0; +} diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h b/drivers/gpu/drm/i915/gt/intel_sa_media.h new file mode 100644 index 000000000000..3afb310de932 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ +#ifndef __INTEL_SA_MEDIA__ +#define __INTEL_SA_MEDIA__ + +#include <linux/types.h> + +struct intel_gt; + +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, + u32 gsi_offset); + +#endif /* __INTEL_SA_MEDIA_H__ */ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 26b25d9434d6..19fc00bcd7b9 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -26,6 +26,9 @@ #include <drm/drm_drv.h> #include <drm/i915_pciids.h> +#include "gt/intel_gt_regs.h" +#include "gt/intel_sa_media.h" + #include "i915_driver.h" #include "i915_drv.h" #include "i915_pci.h" @@ -1115,6 +1118,16 @@ static const struct intel_device_info pvc_info = { .display.has_cdclk_crawl = 1, \ .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) +static const struct intel_gt_definition xelpmp_extra_gt[] = { + { + .type = GT_MEDIA, + .name = "Standalone Media GT", + .gsi_offset = MTL_MEDIA_GSI_BASE, + .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2), + }, + {} +}; + __maybe_unused static const struct intel_device_info mtl_info = { XE_HP_FEATURES, @@ -1128,6 +1141,7 @@ static const struct intel_device_info mtl_info = { .media.ver = 13, PLATFORM(INTEL_METEORLAKE), .display.has_modular_fia = 1, + .extra_gt_list = xelpmp_extra_gt, .has_flat_ccs = 0, .has_snoop = 1, .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, -- 2.37.2
next prev parent reply other threads:[~2022-09-06 23:50 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-06 23:49 [PATCH v3 00/14] i915: Add "standalone media" support for MTL Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-06 23:49 ` [PATCH v3 01/14] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-06 23:49 ` [PATCH v3 02/14] drm/i915: Only hook up uncore->debug for primary uncore Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-06 23:49 ` [PATCH v3 03/14] drm/i915: Use managed allocations for extra uncore objects Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-06 23:49 ` [PATCH v3 04/14] drm/i915: Drop intel_gt_tile_cleanup() Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-07 0:07 ` Lucas De Marchi 2022-09-07 0:07 ` [Intel-gfx] " Lucas De Marchi 2022-09-07 11:18 ` kernel test robot 2022-09-07 11:18 ` [Intel-gfx] " kernel test robot 2022-09-06 23:49 ` [PATCH v3 05/14] drm/i915: Prepare more multi-GT initialization Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-08 16:19 ` Iddamsetty, Aravind 2022-09-08 16:19 ` [Intel-gfx] " Iddamsetty, Aravind 2022-09-06 23:49 ` [Intel-gfx] [PATCH v3 06/14] drm/i915: Rename and expose common GT early init routine Matt Roper 2022-09-06 23:49 ` Matt Roper 2022-09-06 23:49 ` [PATCH v3 07/14] drm/i915: Use a DRM-managed action to release the PCI bridge device Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-09 20:57 ` Sripada, Radhakrishna 2022-09-09 20:57 ` [Intel-gfx] " Sripada, Radhakrishna 2022-09-06 23:49 ` [PATCH v3 08/14] drm/i915: Initialize MMIO access for each GT Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-08 20:52 ` Ceraolo Spurio, Daniele 2022-09-08 20:52 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-09-06 23:49 ` [PATCH v3 09/14] drm/i915: Handle each GT on init/release and suspend/resume Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-08 20:55 ` Ceraolo Spurio, Daniele 2022-09-08 20:55 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-09-06 23:49 ` [PATCH v3 10/14] drm/i915/uncore: Add GSI offset to uncore Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-08 21:16 ` Ceraolo Spurio, Daniele 2022-09-08 21:16 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-09-08 22:29 ` Matt Roper 2022-09-08 22:29 ` [Intel-gfx] " Matt Roper 2022-09-08 22:45 ` [PATCH v3.1 " Matt Roper 2022-09-08 22:45 ` [Intel-gfx] " Matt Roper 2022-09-08 22:53 ` Ceraolo Spurio, Daniele 2022-09-08 22:53 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-09-06 23:49 ` [Intel-gfx] [PATCH v3 11/14] drm/i915/mtl: Add gsi_offset when emitting aux table invalidation Matt Roper 2022-09-06 23:49 ` Matt Roper 2022-09-07 16:16 ` Iddamsetty, Aravind 2022-09-07 16:16 ` [Intel-gfx] " Iddamsetty, Aravind 2022-09-06 23:49 ` Matt Roper [this message] 2022-09-06 23:49 ` [PATCH v3 12/14] drm/i915/xelpmp: Expose media as another GT Matt Roper 2022-09-08 16:22 ` Iddamsetty, Aravind 2022-09-08 16:22 ` [Intel-gfx] " Iddamsetty, Aravind 2022-09-06 23:49 ` [PATCH v3 13/14] drm/i915/mtl: Use primary GT's irq lock for media GT Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-08 21:20 ` Ceraolo Spurio, Daniele 2022-09-08 21:20 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-09-06 23:49 ` [PATCH v3 14/14] drm/i915/mtl: Hook up interrupts for standalone media Matt Roper 2022-09-06 23:49 ` [Intel-gfx] " Matt Roper 2022-09-07 0:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Add "standalone media" support for MTL (rev4) Patchwork 2022-09-07 0:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-09-07 0:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-09-07 4:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-09-07 5:27 ` Matt Roper 2022-09-07 15:46 ` Vudum, Lakshminarayana 2022-09-07 15:27 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork 2022-09-08 23:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Add "standalone media" support for MTL (rev5) Patchwork 2022-09-08 23:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-09-08 23:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-09-09 5:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-09-09 22:21 ` Matt Roper
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