From: "Iddamsetty, Aravind" <aravind.iddamsetty@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: dri-devel@lists.freedesktop.org,
Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Subject: Re: [PATCH v3 05/14] drm/i915: Prepare more multi-GT initialization
Date: Thu, 8 Sep 2022 21:49:02 +0530 [thread overview]
Message-ID: <7c216705-db63-82d7-18bf-6598042f69a6@intel.com> (raw)
In-Reply-To: <20220906234934.3655440-6-matthew.d.roper@intel.com>
On 07-09-2022 05:19, Matt Roper wrote:
> We're going to introduce an additional intel_gt for MTL's media unit
> soon. Let's provide a bit more multi-GT initialization framework in
> preparation for that. The initialization will pull the list of GTs for
> a platform from the device info structure. Although necessary for the
> immediate MTL media enabling, this same framework will also be used
> farther down the road when we enable remote tiles on xehpsdv and pvc.
>
> v2:
> - Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
>
> v3:
> - Move intel_gt_definition struct to intel_gt_types.h. (Jani)
> - Drop gtdef->setup(). For now we'll just use a switch() based on GT
> type since we don't have too many different handlers for the
> forseeable future. (Jani)
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 59 ++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 15 +++++
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 3 +
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 7 files changed, 80 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..41acc285e8bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> u16 vdbox_mask;
> u16 vebox_mask;
>
> - info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> + GEM_BUG_ON(!info->engine_mask);
>
> if (GRAPHICS_VER(i915) < 11)
> return info->engine_mask;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 663a4798fb2e..85c75375391c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -807,8 +807,10 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> {
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct intel_gt *gt = &i915->gt0;
> + const struct intel_gt_definition *gtdef;
> phys_addr_t phys_addr;
> unsigned int mmio_bar;
> + unsigned int i;
> int ret;
>
> mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
> @@ -819,14 +821,69 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> * and it has been already initialized early during probe
> * in i915_driver_probe()
> */
> + gt->i915 = i915;
> + gt->name = "Primary GT";
> + gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> +
> + drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> ret = intel_gt_tile_setup(gt, phys_addr);
> if (ret)
> return ret;
>
> i915->gt[0] = gt;
>
> - /* TODO: add more tiles */
> + if (!HAS_EXTRA_GT_LIST(i915))
> + return 0;
> +
> + for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
> + gtdef->name != NULL;
> + i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
> + gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
> + if (!gt) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + gt->i915 = i915;
> + gt->name = gtdef->name;
> + gt->type = gtdef->type;
> + gt->info.engine_mask = gtdef->engine_mask;
> + gt->info.id = i;
> +
> + drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + if (GEM_WARN_ON(range_overflows_t(resource_size_t,
> + gtdef->mapping_base,
> + SZ_16M,
> + pci_resource_len(pdev, mmio_bar)))) {
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + switch (gtdef->type) {
> + case GT_TILE:
> + ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base);
> + break;
> +
> + case GT_PRIMARY:
> + /* Primary GT should not appear in extra GT list */
> + default:
> + MISSING_CASE(gtdef->type);
> + ret = -ENODEV;
> + }
> +
> + if (ret)
> + goto err;
> +
> + i915->gt[i] = gt;
> + }
> +
> return 0;
> +
> +err:
> + i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
> + intel_gt_release_all(i915);
> +
> + return ret;
> }
>
> int intel_gt_tiles_init(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 40b06adf509a..4d8779529cc2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
> void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
> -
> void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 4d56f7d5a3be..0e139f7d75ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -81,8 +81,16 @@ struct gt_defaults {
> u32 max_freq;
> };
>
> +enum intel_gt_type {
> + GT_PRIMARY,
> + GT_TILE,
> +};
> +
> struct intel_gt {
> struct drm_i915_private *i915;
> + const char *name;
> + enum intel_gt_type type;
> +
> struct intel_uncore *uncore;
> struct i915_ggtt *ggtt;
>
> @@ -262,6 +270,13 @@ struct intel_gt {
> struct kobject *sysfs_defaults;
> };
>
> +struct intel_gt_definition {
> + enum intel_gt_type type;
> + char *name;
> + u32 mapping_base;
> + intel_engine_mask_t engine_mask;
> +};
> +
> enum intel_gt_scratch_field {
> /* 8 bytes */
> INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index befb167b3c49..f010be8df851 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -916,6 +916,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>
> +#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
> +
> /*
> * Platform has the dedicated compression control state for each lmem surfaces
> * stored in lmem to support the 3D and media compression formats.
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6904ad03ca19..deaa07d8df2c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -37,6 +37,7 @@
>
> struct drm_printer;
> struct drm_i915_private;
> +struct intel_gt_definition;
>
> /* Keep in gen based order, and chronological order within a gen */
> enum intel_platform {
> @@ -252,6 +253,8 @@ struct intel_device_info {
>
> unsigned int dma_mask_size; /* available DMA address bits */
>
> + const struct intel_gt_definition *extra_gt_list;
> +
> u8 gt; /* GT number, 0 if undefined */
>
> #define DEFINE_FLAG(name) u8 name:1
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index f5904e659ef2..915d58ba383e 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -115,6 +115,7 @@ static struct dev_pm_domain pm_domain = {
> static void mock_gt_probe(struct drm_i915_private *i915)
> {
> i915->gt[0] = &i915->gt0;
> + i915->gt[0]->name = "Mock GT";
> }
>
> struct drm_i915_private *mock_gem_device(void)
LGTM.
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Aravind.
WARNING: multiple messages have this Message-ID (diff)
From: "Iddamsetty, Aravind" <aravind.iddamsetty@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 05/14] drm/i915: Prepare more multi-GT initialization
Date: Thu, 8 Sep 2022 21:49:02 +0530 [thread overview]
Message-ID: <7c216705-db63-82d7-18bf-6598042f69a6@intel.com> (raw)
In-Reply-To: <20220906234934.3655440-6-matthew.d.roper@intel.com>
On 07-09-2022 05:19, Matt Roper wrote:
> We're going to introduce an additional intel_gt for MTL's media unit
> soon. Let's provide a bit more multi-GT initialization framework in
> preparation for that. The initialization will pull the list of GTs for
> a platform from the device info structure. Although necessary for the
> immediate MTL media enabling, this same framework will also be used
> farther down the road when we enable remote tiles on xehpsdv and pvc.
>
> v2:
> - Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
>
> v3:
> - Move intel_gt_definition struct to intel_gt_types.h. (Jani)
> - Drop gtdef->setup(). For now we'll just use a switch() based on GT
> type since we don't have too many different handlers for the
> forseeable future. (Jani)
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 59 ++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 15 +++++
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 3 +
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 7 files changed, 80 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..41acc285e8bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> u16 vdbox_mask;
> u16 vebox_mask;
>
> - info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> + GEM_BUG_ON(!info->engine_mask);
>
> if (GRAPHICS_VER(i915) < 11)
> return info->engine_mask;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 663a4798fb2e..85c75375391c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -807,8 +807,10 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> {
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct intel_gt *gt = &i915->gt0;
> + const struct intel_gt_definition *gtdef;
> phys_addr_t phys_addr;
> unsigned int mmio_bar;
> + unsigned int i;
> int ret;
>
> mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
> @@ -819,14 +821,69 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> * and it has been already initialized early during probe
> * in i915_driver_probe()
> */
> + gt->i915 = i915;
> + gt->name = "Primary GT";
> + gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> +
> + drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> ret = intel_gt_tile_setup(gt, phys_addr);
> if (ret)
> return ret;
>
> i915->gt[0] = gt;
>
> - /* TODO: add more tiles */
> + if (!HAS_EXTRA_GT_LIST(i915))
> + return 0;
> +
> + for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
> + gtdef->name != NULL;
> + i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
> + gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
> + if (!gt) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + gt->i915 = i915;
> + gt->name = gtdef->name;
> + gt->type = gtdef->type;
> + gt->info.engine_mask = gtdef->engine_mask;
> + gt->info.id = i;
> +
> + drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + if (GEM_WARN_ON(range_overflows_t(resource_size_t,
> + gtdef->mapping_base,
> + SZ_16M,
> + pci_resource_len(pdev, mmio_bar)))) {
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + switch (gtdef->type) {
> + case GT_TILE:
> + ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base);
> + break;
> +
> + case GT_PRIMARY:
> + /* Primary GT should not appear in extra GT list */
> + default:
> + MISSING_CASE(gtdef->type);
> + ret = -ENODEV;
> + }
> +
> + if (ret)
> + goto err;
> +
> + i915->gt[i] = gt;
> + }
> +
> return 0;
> +
> +err:
> + i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
> + intel_gt_release_all(i915);
> +
> + return ret;
> }
>
> int intel_gt_tiles_init(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 40b06adf509a..4d8779529cc2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
> void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
> -
> void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 4d56f7d5a3be..0e139f7d75ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -81,8 +81,16 @@ struct gt_defaults {
> u32 max_freq;
> };
>
> +enum intel_gt_type {
> + GT_PRIMARY,
> + GT_TILE,
> +};
> +
> struct intel_gt {
> struct drm_i915_private *i915;
> + const char *name;
> + enum intel_gt_type type;
> +
> struct intel_uncore *uncore;
> struct i915_ggtt *ggtt;
>
> @@ -262,6 +270,13 @@ struct intel_gt {
> struct kobject *sysfs_defaults;
> };
>
> +struct intel_gt_definition {
> + enum intel_gt_type type;
> + char *name;
> + u32 mapping_base;
> + intel_engine_mask_t engine_mask;
> +};
> +
> enum intel_gt_scratch_field {
> /* 8 bytes */
> INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index befb167b3c49..f010be8df851 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -916,6 +916,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>
> +#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
> +
> /*
> * Platform has the dedicated compression control state for each lmem surfaces
> * stored in lmem to support the 3D and media compression formats.
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6904ad03ca19..deaa07d8df2c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -37,6 +37,7 @@
>
> struct drm_printer;
> struct drm_i915_private;
> +struct intel_gt_definition;
>
> /* Keep in gen based order, and chronological order within a gen */
> enum intel_platform {
> @@ -252,6 +253,8 @@ struct intel_device_info {
>
> unsigned int dma_mask_size; /* available DMA address bits */
>
> + const struct intel_gt_definition *extra_gt_list;
> +
> u8 gt; /* GT number, 0 if undefined */
>
> #define DEFINE_FLAG(name) u8 name:1
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index f5904e659ef2..915d58ba383e 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -115,6 +115,7 @@ static struct dev_pm_domain pm_domain = {
> static void mock_gt_probe(struct drm_i915_private *i915)
> {
> i915->gt[0] = &i915->gt0;
> + i915->gt[0]->name = "Mock GT";
> }
>
> struct drm_i915_private *mock_gem_device(void)
LGTM.
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Aravind.
next prev parent reply other threads:[~2022-09-08 16:19 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 23:49 [PATCH v3 00/14] i915: Add "standalone media" support for MTL Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-06 23:49 ` [PATCH v3 01/14] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-06 23:49 ` [PATCH v3 02/14] drm/i915: Only hook up uncore->debug for primary uncore Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-06 23:49 ` [PATCH v3 03/14] drm/i915: Use managed allocations for extra uncore objects Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-06 23:49 ` [PATCH v3 04/14] drm/i915: Drop intel_gt_tile_cleanup() Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-07 0:07 ` Lucas De Marchi
2022-09-07 0:07 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 11:18 ` kernel test robot
2022-09-07 11:18 ` [Intel-gfx] " kernel test robot
2022-09-06 23:49 ` [PATCH v3 05/14] drm/i915: Prepare more multi-GT initialization Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-08 16:19 ` Iddamsetty, Aravind [this message]
2022-09-08 16:19 ` Iddamsetty, Aravind
2022-09-06 23:49 ` [Intel-gfx] [PATCH v3 06/14] drm/i915: Rename and expose common GT early init routine Matt Roper
2022-09-06 23:49 ` Matt Roper
2022-09-06 23:49 ` [PATCH v3 07/14] drm/i915: Use a DRM-managed action to release the PCI bridge device Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-09 20:57 ` Sripada, Radhakrishna
2022-09-09 20:57 ` [Intel-gfx] " Sripada, Radhakrishna
2022-09-06 23:49 ` [PATCH v3 08/14] drm/i915: Initialize MMIO access for each GT Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-08 20:52 ` Ceraolo Spurio, Daniele
2022-09-08 20:52 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-06 23:49 ` [PATCH v3 09/14] drm/i915: Handle each GT on init/release and suspend/resume Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-08 20:55 ` Ceraolo Spurio, Daniele
2022-09-08 20:55 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-06 23:49 ` [PATCH v3 10/14] drm/i915/uncore: Add GSI offset to uncore Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-08 21:16 ` Ceraolo Spurio, Daniele
2022-09-08 21:16 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-08 22:29 ` Matt Roper
2022-09-08 22:29 ` [Intel-gfx] " Matt Roper
2022-09-08 22:45 ` [PATCH v3.1 " Matt Roper
2022-09-08 22:45 ` [Intel-gfx] " Matt Roper
2022-09-08 22:53 ` Ceraolo Spurio, Daniele
2022-09-08 22:53 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-06 23:49 ` [Intel-gfx] [PATCH v3 11/14] drm/i915/mtl: Add gsi_offset when emitting aux table invalidation Matt Roper
2022-09-06 23:49 ` Matt Roper
2022-09-07 16:16 ` Iddamsetty, Aravind
2022-09-07 16:16 ` [Intel-gfx] " Iddamsetty, Aravind
2022-09-06 23:49 ` [Intel-gfx] [PATCH v3 12/14] drm/i915/xelpmp: Expose media as another GT Matt Roper
2022-09-06 23:49 ` Matt Roper
2022-09-08 16:22 ` Iddamsetty, Aravind
2022-09-08 16:22 ` [Intel-gfx] " Iddamsetty, Aravind
2022-09-06 23:49 ` [PATCH v3 13/14] drm/i915/mtl: Use primary GT's irq lock for media GT Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-08 21:20 ` Ceraolo Spurio, Daniele
2022-09-08 21:20 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-06 23:49 ` [PATCH v3 14/14] drm/i915/mtl: Hook up interrupts for standalone media Matt Roper
2022-09-06 23:49 ` [Intel-gfx] " Matt Roper
2022-09-07 0:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Add "standalone media" support for MTL (rev4) Patchwork
2022-09-07 0:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-07 0:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-07 4:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-07 5:27 ` Matt Roper
2022-09-07 15:46 ` Vudum, Lakshminarayana
2022-09-07 15:27 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-09-08 23:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Add "standalone media" support for MTL (rev5) Patchwork
2022-09-08 23:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-08 23:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-09 5:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-09 22:21 ` Matt Roper
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