From: Prabhakar <prabhakar.csengg@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: Heiko Stuebner <heiko@sntech.de>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atishp@rivosinc.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically
Date: Tue, 20 Sep 2022 19:48:56 +0100 [thread overview]
Message-ID: <20220920184904.90495-3-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
v3 -> v4
* Included RB tag from Heiko
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included RB tag from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Prabhakar <prabhakar.csengg@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: Heiko Stuebner <heiko@sntech.de>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atishp@rivosinc.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically
Date: Tue, 20 Sep 2022 19:48:56 +0100 [thread overview]
Message-ID: <20220920184904.90495-3-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
v3 -> v4
* Included RB tag from Heiko
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included RB tag from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.25.1
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next prev parent reply other threads:[~2022-09-20 18:50 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-10-28 12:44 ` Geert Uytterhoeven
2022-10-28 12:44 ` Geert Uytterhoeven
2022-09-20 18:48 ` Prabhakar [this message]
2022-09-20 18:48 ` [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-20 18:48 ` [PATCH v4 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-10-28 12:46 ` Geert Uytterhoeven
2022-10-28 12:46 ` Geert Uytterhoeven
2022-09-20 18:48 ` [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 19:04 ` Conor Dooley
2022-09-20 19:04 ` Conor Dooley
2022-09-20 21:04 ` Lad, Prabhakar
2022-09-20 21:04 ` Lad, Prabhakar
2022-09-20 21:10 ` Conor Dooley
2022-09-20 21:10 ` Conor Dooley
2022-09-20 18:49 ` [PATCH v4 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 19:21 ` Biju Das
2022-09-20 19:21 ` Biju Das
2022-09-20 19:26 ` Biju Das
2022-09-20 19:26 ` Biju Das
2022-09-20 20:51 ` Lad, Prabhakar
2022-09-20 20:51 ` Lad, Prabhakar
2022-09-21 5:22 ` Biju Das
2022-09-21 5:22 ` Biju Das
2022-09-21 7:49 ` Geert Uytterhoeven
2022-09-21 7:49 ` Geert Uytterhoeven
2022-09-20 18:49 ` [PATCH v4 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 10/10] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 19:20 ` [PATCH v4 00/10] Add support for " Conor Dooley
2022-09-20 19:20 ` Conor Dooley
2022-09-20 19:24 ` Geert Uytterhoeven
2022-09-20 19:24 ` Geert Uytterhoeven
2022-09-20 19:37 ` Conor Dooley
2022-09-20 19:37 ` Conor Dooley
2022-09-20 20:43 ` Lad, Prabhakar
2022-09-20 20:43 ` Lad, Prabhakar
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