From: Biju Das <biju.das.jz@bp.renesas.com>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atishp@rivosinc.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
Date: Wed, 21 Sep 2022 05:22:23 +0000 [thread overview]
Message-ID: <OS0PR01MB59220E0803C83EC63954340E864F9@OS0PR01MB5922.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CA+V-a8s-6FLu-5D44-Szt8eN1V0rhPxm+cO4OrcKmT90O8LoXg@mail.gmail.com>
Hi Prabhakar,
> Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
>
> Hi Biju,
>
> On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> >
> > Just ignore my mail, As I realised IRQ property in each node will be
> a problem.
> >
> Yes the IRQ numbers are different (offset of 32) along with the IRQ
> parent.
>
> Refer this thread [0] where other SoC vendors have similar issues,
> maybe in future when DTC becomes more clever we can use single SoC
> DTSI for both.
Not sure, May be the macro suggestion mentioned in that thread will work for us??
As it is just only the interrupt properties that differ which is
handled in macro. A Generic macro in common dtsi which is
expanded in RISCV or arm64 specific dtsi to get proper one??
Cheers,
Biju
WARNING: multiple messages have this Message-ID (diff)
From: Biju Das <biju.das.jz@bp.renesas.com>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atishp@rivosinc.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
Date: Wed, 21 Sep 2022 05:22:23 +0000 [thread overview]
Message-ID: <OS0PR01MB59220E0803C83EC63954340E864F9@OS0PR01MB5922.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CA+V-a8s-6FLu-5D44-Szt8eN1V0rhPxm+cO4OrcKmT90O8LoXg@mail.gmail.com>
Hi Prabhakar,
> Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
>
> Hi Biju,
>
> On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> >
> > Just ignore my mail, As I realised IRQ property in each node will be
> a problem.
> >
> Yes the IRQ numbers are different (offset of 32) along with the IRQ
> parent.
>
> Refer this thread [0] where other SoC vendors have similar issues,
> maybe in future when DTC becomes more clever we can use single SoC
> DTSI for both.
Not sure, May be the macro suggestion mentioned in that thread will work for us??
As it is just only the interrupt properties that differ which is
handled in macro. A Generic macro in common dtsi which is
expanded in RISCV or arm64 specific dtsi to get proper one??
Cheers,
Biju
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-21 5:22 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-10-28 12:44 ` Geert Uytterhoeven
2022-10-28 12:44 ` Geert Uytterhoeven
2022-09-20 18:48 ` [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-10-28 12:46 ` Geert Uytterhoeven
2022-10-28 12:46 ` Geert Uytterhoeven
2022-09-20 18:48 ` [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
2022-09-20 18:48 ` Prabhakar
2022-09-20 19:04 ` Conor Dooley
2022-09-20 19:04 ` Conor Dooley
2022-09-20 21:04 ` Lad, Prabhakar
2022-09-20 21:04 ` Lad, Prabhakar
2022-09-20 21:10 ` Conor Dooley
2022-09-20 21:10 ` Conor Dooley
2022-09-20 18:49 ` [PATCH v4 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 19:21 ` Biju Das
2022-09-20 19:21 ` Biju Das
2022-09-20 19:26 ` Biju Das
2022-09-20 19:26 ` Biju Das
2022-09-20 20:51 ` Lad, Prabhakar
2022-09-20 20:51 ` Lad, Prabhakar
2022-09-21 5:22 ` Biju Das [this message]
2022-09-21 5:22 ` Biju Das
2022-09-21 7:49 ` Geert Uytterhoeven
2022-09-21 7:49 ` Geert Uytterhoeven
2022-09-20 18:49 ` [PATCH v4 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 10/10] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-09-20 18:49 ` Prabhakar
2022-09-20 19:20 ` [PATCH v4 00/10] Add support for " Conor Dooley
2022-09-20 19:20 ` Conor Dooley
2022-09-20 19:24 ` Geert Uytterhoeven
2022-09-20 19:24 ` Geert Uytterhoeven
2022-09-20 19:37 ` Conor Dooley
2022-09-20 19:37 ` Conor Dooley
2022-09-20 20:43 ` Lad, Prabhakar
2022-09-20 20:43 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=OS0PR01MB59220E0803C83EC63954340E864F9@OS0PR01MB5922.jpnprd01.prod.outlook.com \
--to=biju.das.jz@bp.renesas.com \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@rivosinc.com \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=heiko@sntech.de \
--cc=heinrich.schuchardt@canonical.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=magnus.damm@gmail.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.csengg@gmail.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.