From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, yangyingliang@huawei.com, msp@baylibre.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/10] clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks Date: Mon, 24 Oct 2022 12:22:58 +0200 [thread overview] Message-ID: <20221024102307.33722-2-angelogioacchino.delregno@collabora.com> (raw) In-Reply-To: <20221024102307.33722-1-angelogioacchino.delregno@collabora.com> Before this change, every mtk_fixed_factor clock forced clock flags to CLK_SET_RATE_PARENT: while this is harmless in some cases, it may not be desired in some others, especially when performing clock muxing on a clock having multiple parents of which one is a dedicated PLL and the others are not. This is especially seen on the GPU clocks on some SoCs, where we are muxing between multiple parents: a fixed clock (crystal), a programmable GPU PLL and one or more dividers for the MAINPLL, used for a number of devices; it happens that when a rate change is called for the GPU, the clock framework will try to satisfy the rate request by using one of the MAINPLL dividers, which have CLK_SET_RATE_PARENT and will set the rate on MAINPLL itself - overclocking or underclocking many devices in the system - and making it to lock up. Logically, it should be harmless (and would only reduce possible bugs) to change all of the univpll and mainpll related fixed factor clocks to not declare the CLK_SET_RATE_PARENT by default but, on some SoCs, this is also used for dividers of other PLLs for which a rate change based on the divider may be desired, hence introduce a new FACTOR_FLAGS() macro to use custom flags (or none) on selected fixed factor clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-mtk.h | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d31f01d0ba1c..3c1ac8d3010f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -149,7 +149,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, } hw = clk_hw_register_fixed_factor(NULL, ff->name, ff->parent_name, - CLK_SET_RATE_PARENT, ff->mult, ff->div); + ff->flags, ff->mult, ff->div); if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", ff->name, diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 63ae7941aa92..f2db6b57d5b5 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -47,16 +47,21 @@ struct mtk_fixed_factor { const char *parent_name; int mult; int div; + unsigned long flags; }; -#define FACTOR(_id, _name, _parent, _mult, _div) { \ +#define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \ .id = _id, \ .name = _name, \ .parent_name = _parent, \ .mult = _mult, \ .div = _div, \ + .flags = _fl, \ } +#define FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT) + int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, struct clk_hw_onecell_data *clk_data); void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, yangyingliang@huawei.com, msp@baylibre.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/10] clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks Date: Mon, 24 Oct 2022 12:22:58 +0200 [thread overview] Message-ID: <20221024102307.33722-2-angelogioacchino.delregno@collabora.com> (raw) In-Reply-To: <20221024102307.33722-1-angelogioacchino.delregno@collabora.com> Before this change, every mtk_fixed_factor clock forced clock flags to CLK_SET_RATE_PARENT: while this is harmless in some cases, it may not be desired in some others, especially when performing clock muxing on a clock having multiple parents of which one is a dedicated PLL and the others are not. This is especially seen on the GPU clocks on some SoCs, where we are muxing between multiple parents: a fixed clock (crystal), a programmable GPU PLL and one or more dividers for the MAINPLL, used for a number of devices; it happens that when a rate change is called for the GPU, the clock framework will try to satisfy the rate request by using one of the MAINPLL dividers, which have CLK_SET_RATE_PARENT and will set the rate on MAINPLL itself - overclocking or underclocking many devices in the system - and making it to lock up. Logically, it should be harmless (and would only reduce possible bugs) to change all of the univpll and mainpll related fixed factor clocks to not declare the CLK_SET_RATE_PARENT by default but, on some SoCs, this is also used for dividers of other PLLs for which a rate change based on the divider may be desired, hence introduce a new FACTOR_FLAGS() macro to use custom flags (or none) on selected fixed factor clocks. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-mtk.h | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d31f01d0ba1c..3c1ac8d3010f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -149,7 +149,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, } hw = clk_hw_register_fixed_factor(NULL, ff->name, ff->parent_name, - CLK_SET_RATE_PARENT, ff->mult, ff->div); + ff->flags, ff->mult, ff->div); if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", ff->name, diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 63ae7941aa92..f2db6b57d5b5 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -47,16 +47,21 @@ struct mtk_fixed_factor { const char *parent_name; int mult; int div; + unsigned long flags; }; -#define FACTOR(_id, _name, _parent, _mult, _div) { \ +#define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \ .id = _id, \ .name = _name, \ .parent_name = _parent, \ .mult = _mult, \ .div = _div, \ + .flags = _fl, \ } +#define FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT) + int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, struct clk_hw_onecell_data *clk_data); void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, -- 2.37.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-10-24 10:23 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-24 10:22 [PATCH 00/10] MTK: Undesired set_rate on main PLLs and GPU DVFS AngeloGioacchino Del Regno 2022-10-24 10:22 ` AngeloGioacchino Del Regno 2022-10-24 10:22 ` AngeloGioacchino Del Regno [this message] 2022-10-24 10:22 ` [PATCH 01/10] clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks AngeloGioacchino Del Regno 2022-10-24 21:57 ` Chen-Yu Tsai 2022-10-24 21:57 ` Chen-Yu Tsai 2022-10-24 10:22 ` [PATCH 02/10] clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors AngeloGioacchino Del Regno 2022-10-24 10:22 ` AngeloGioacchino Del Regno 2022-10-24 21:58 ` Chen-Yu Tsai 2022-10-24 21:58 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 03/10] clk: mediatek: mt8183: Compress top_divs array entries AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:02 ` Chen-Yu Tsai 2022-10-24 22:02 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 04/10] clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:05 ` Chen-Yu Tsai 2022-10-24 22:05 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 05/10] clk: mediatek: mt8173: Drop flags for main/sys/univpll " AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:06 ` Chen-Yu Tsai 2022-10-24 22:06 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 06/10] clk: mediatek: mt6795-topckgen: " AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:09 ` Chen-Yu Tsai 2022-10-24 22:09 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 07/10] clk: mediatek: mt8192: Drop flags for main/univpll " AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:10 ` Chen-Yu Tsai 2022-10-24 22:10 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 08/10] clk: mediatek: mt8195-topckgen: " AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:10 ` Chen-Yu Tsai 2022-10-24 22:10 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 09/10] clk: mediatek: mt8186-mfg: Propagate rate changes to parent AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:11 ` Chen-Yu Tsai 2022-10-24 22:11 ` Chen-Yu Tsai 2022-10-24 10:23 ` [PATCH 10/10] clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier AngeloGioacchino Del Regno 2022-10-24 10:23 ` AngeloGioacchino Del Regno 2022-10-24 22:12 ` Chen-Yu Tsai 2022-10-24 22:12 ` Chen-Yu Tsai 2022-11-29 7:03 ` [PATCH 00/10] MTK: Undesired set_rate on main PLLs and GPU DVFS Chen-Yu Tsai 2022-11-29 7:03 ` Chen-Yu Tsai
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20221024102307.33722-2-angelogioacchino.delregno@collabora.com \ --to=angelogioacchino.delregno@collabora.com \ --cc=chun-jie.chen@mediatek.com \ --cc=jose.exposito89@gmail.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mediatek@lists.infradead.org \ --cc=matthias.bgg@gmail.com \ --cc=miles.chen@mediatek.com \ --cc=msp@baylibre.com \ --cc=mturquette@baylibre.com \ --cc=nfraprado@collabora.com \ --cc=rex-bc.chen@mediatek.com \ --cc=sboyd@kernel.org \ --cc=wenst@chromium.org \ --cc=yangyingliang@huawei.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.