Re: [PATCH 05/10] clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors - Chen-Yu Tsai

From: Chen-Yu Tsai <wenst@chromium.org>
To: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
Cc: sboyd@kernel.org, mturquette@baylibre.com,
	matthias.bgg@gmail.com, miles.chen@mediatek.com,
	nfraprado@collabora.com, rex-bc.chen@mediatek.com,
	chun-jie.chen@mediatek.com, jose.exposito89@gmail.com,
	yangyingliang@huawei.com, msp@baylibre.com,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/10] clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
Date: Mon, 24 Oct 2022 15:06:35 -0700	[thread overview]
Message-ID: <CAGXv+5EwrRqNuqunzLHtRyZ+AMyO1DDwP01TC9CjbxHnRxbH0g@mail.gmail.com> (raw)
In-Reply-To: <20221024102307.33722-6-angelogioacchino.delregno@collabora.com>

On Mon, Oct 24, 2022 at 3:23 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> The main/sys/univpll clocks are used as clock sources for multiple
> peripherals of different kind, some of which are critical (like AXIs);
> a rate change on any of these two will produce a rate change on many
> devices and that's likely to produce system instability if not done
> correctly: this is the reason why we have (a lot of) "fixed factor"
> main/sys/univpll divider clocks, used by MUX clocks to provide
> different rates based on PLL output dividers.
>
> Following what was done on clk-mt8186-topckgen and also preventing the
> same GPU DVFS issue, drop CLK_SET_RATE_PARENT from the aforementioned
> clocks.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>