[PATCH V2 0/6] Xilinx DMA enhancements and optimization

From: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <lars@metafoo.de>,
	<adrianml@alumnos.upm.es>
Cc: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,
	<radhey.shyam.pandey@amd.com>, <anirudha.sarangi@amd.com>,
	<harini.katakam@amd.com>, <sarath.babu.naidu.gaddam@amd.com>,
	<git@amd.com>
Subject: [PATCH V2 0/6] Xilinx DMA enhancements and optimization
Date: Thu, 24 Nov 2022 15:57:39 +0530	[thread overview]
Message-ID: <20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com> (raw)

Some background about the patch series: Xilinx Axi Ethernet device driver
(xilinx_axienet_main.c) currently has axi-dma code inside it. The goal is
to refactor axiethernet driver and use existing AXI DMA driver using
DMAEngine API.

This patchset does feature addition and optimization to support axidma
integration with axiethernet network driver. Once axidma version is
accepted mcdma specific changes will be added in followup version.

Changes in V2: 
1) Moved xlnx,axistream-connected optional property to under AXI DMA.
2) Removed Acked-by: Rob Herringi for PATCH 1/6.
3) New patch(6/6).

Comments, suggestions are very welcome!

Radhey Shyam Pandey (6):
  dt-bindings: dmaengine: xilinx_dma:Add xlnx,axistream-connected
    property
  dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
  dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
  dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
  dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
    usecase
  dmaengine: xilinx_dma: Program interrupt delay timeout

 .../bindings/dma/xilinx/xilinx_dma.txt        |  6 ++
 drivers/dma/xilinx/xilinx_dma.c               | 61 +++++++++++++++----
 2 files changed, 56 insertions(+), 11 deletions(-)

-- 
2.25.1