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From: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <lars@metafoo.de>,
	<adrianml@alumnos.upm.es>
Cc: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,
	<radhey.shyam.pandey@amd.com>, <anirudha.sarangi@amd.com>,
	<harini.katakam@amd.com>, <sarath.babu.naidu.gaddam@amd.com>,
	<git@amd.com>
Subject: [PATCH V2 1/6] dt-bindings: dmaengine: xilinx_dma:Add xlnx,axistream-connected property
Date: Thu, 24 Nov 2022 15:57:40 +0530	[thread overview]
Message-ID: <20221124102745.2620370-2-sarath.babu.naidu.gaddam@amd.com> (raw)
In-Reply-To: <20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com>

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Add an optional AXI DMA property 'xlnx,axistream-connected'. This
can be specified to indicate that DMA is connected to a streaming IP
in the hardware design and dma driver needs to do some additional
handling i.e pass metadata and perform streaming IP specific
configuration.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V2:
1) Moved xlnx,axistream-connected optional property to under AXI DMA.
2) Removed Acked-by: Rob Herring.
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index d1700a5c36bf..fea5b09a439d 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -49,6 +49,10 @@ Optional properties for AXI DMA and MCDMA:
 	register as configured in h/w. Takes values {8...26}. If the property
 	is missing or invalid then the default value 23 is used. This is the
 	maximum value that is supported by all IP versions.
+
+Optional properties for AXI DMA:
+- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
+
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <lars@metafoo.de>,
	<adrianml@alumnos.upm.es>
Cc: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,
	<radhey.shyam.pandey@amd.com>, <anirudha.sarangi@amd.com>,
	<harini.katakam@amd.com>, <sarath.babu.naidu.gaddam@amd.com>,
	<git@amd.com>
Subject: [PATCH V2 1/6] dt-bindings: dmaengine: xilinx_dma:Add xlnx,axistream-connected property
Date: Thu, 24 Nov 2022 15:57:40 +0530	[thread overview]
Message-ID: <20221124102745.2620370-2-sarath.babu.naidu.gaddam@amd.com> (raw)
In-Reply-To: <20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com>

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Add an optional AXI DMA property 'xlnx,axistream-connected'. This
can be specified to indicate that DMA is connected to a streaming IP
in the hardware design and dma driver needs to do some additional
handling i.e pass metadata and perform streaming IP specific
configuration.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V2:
1) Moved xlnx,axistream-connected optional property to under AXI DMA.
2) Removed Acked-by: Rob Herring.
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index d1700a5c36bf..fea5b09a439d 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -49,6 +49,10 @@ Optional properties for AXI DMA and MCDMA:
 	register as configured in h/w. Takes values {8...26}. If the property
 	is missing or invalid then the default value 23 is used. This is the
 	maximum value that is supported by all IP versions.
+
+Optional properties for AXI DMA:
+- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
+
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1


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  reply	other threads:[~2022-11-24 10:28 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24 10:27 [PATCH V2 0/6] Xilinx DMA enhancements and optimization Sarath Babu Naidu Gaddam
2022-11-24 10:27 ` Sarath Babu Naidu Gaddam
2022-11-24 10:27 ` Sarath Babu Naidu Gaddam [this message]
2022-11-24 10:27   ` [PATCH V2 1/6] dt-bindings: dmaengine: xilinx_dma:Add xlnx,axistream-connected property Sarath Babu Naidu Gaddam
2022-11-26 14:32   ` Krzysztof Kozlowski
2022-11-26 14:32     ` Krzysztof Kozlowski
2022-11-30 21:27     ` Rob Herring
2022-11-30 21:27       ` Rob Herring
2022-11-30 21:27   ` Rob Herring
2022-11-30 21:27     ` Rob Herring
2022-11-24 10:27 ` [PATCH V2 2/6] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Sarath Babu Naidu Gaddam
2022-11-24 10:27   ` Sarath Babu Naidu Gaddam
2022-11-24 10:27 ` [PATCH V2 3/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client Sarath Babu Naidu Gaddam
2022-11-24 10:27   ` Sarath Babu Naidu Gaddam
2022-12-28 11:00   ` Vinod Koul
2022-12-28 11:00     ` Vinod Koul
2023-02-02  7:39     ` Gaddam, Sarath Babu Naidu
2023-02-02  7:39       ` Gaddam, Sarath Babu Naidu
2022-11-24 10:27 ` [PATCH V2 4/6] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Sarath Babu Naidu Gaddam
2022-11-24 10:27   ` Sarath Babu Naidu Gaddam
2022-11-24 10:27 ` [PATCH V2 5/6] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Sarath Babu Naidu Gaddam
2022-11-24 10:27   ` Sarath Babu Naidu Gaddam
2022-11-24 10:27 ` [PATCH V2 6/6] dmaengine: xilinx_dma: Program interrupt delay timeout Sarath Babu Naidu Gaddam
2022-11-24 10:27   ` Sarath Babu Naidu Gaddam
2022-12-28 11:00   ` Vinod Koul
2022-12-28 11:00     ` Vinod Koul
2023-02-02  7:52     ` Gaddam, Sarath Babu Naidu
2023-02-02  7:52       ` Gaddam, Sarath Babu Naidu

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