From: Marek Vasut <marex@denx.de>
To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>, Peng Fan <peng.fan@nxp.com>,
Adam Ford <aford173@gmail.com>, Alice Guo <alice.guo@nxp.com>,
Amit Kucheria <amitk@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Jun <jun.li@nxp.com>, Lucas Stach <l.stach@pengutronix.de>,
Markus Niebel <Markus.Niebel@ew.tq-group.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Zhang Rui <rui.zhang@intel.com>,
devicetree@vger.kernel.org
Subject: [PATCH v2 3/5] arm64: dts: imx8m: Document the fuse address calculation
Date: Thu, 1 Dec 2022 22:56:49 +0100 [thread overview]
Message-ID: <20221201215651.152497-3-marex@denx.de> (raw)
In-Reply-To: <20221201215651.152497-1-marex@denx.de>
The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to find
out how it works. No functional change.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
V2: Add RB from Peng
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++----
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++---
4 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 423cb36cbcd53..513c2de0caa15 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -563,15 +563,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 312e3abc35ea8..068f599cdf757 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -564,15 +564,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mn_uid: unique-id@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9459ed21b243..ddcd5e23ba47d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -426,19 +426,32 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mp_uid: unique-id@8 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x8 0x8> describes fuses 0x420 and
+ * 0x430).
+ */
+ imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- eth_mac1: mac-address@90 {
+ eth_mac1: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
- eth_mac2: mac-address@96 {
+ eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2b6d3f4ff5d93..8a2ec90b493d9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -593,15 +593,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mq_uid: soc-uid@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
--
2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Marek Vasut <marex@denx.de>
To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>, Peng Fan <peng.fan@nxp.com>,
Adam Ford <aford173@gmail.com>, Alice Guo <alice.guo@nxp.com>,
Amit Kucheria <amitk@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Jun <jun.li@nxp.com>, Lucas Stach <l.stach@pengutronix.de>,
Markus Niebel <Markus.Niebel@ew.tq-group.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Zhang Rui <rui.zhang@intel.com>,
devicetree@vger.kernel.org
Subject: [PATCH v2 3/5] arm64: dts: imx8m: Document the fuse address calculation
Date: Thu, 1 Dec 2022 22:56:49 +0100 [thread overview]
Message-ID: <20221201215651.152497-3-marex@denx.de> (raw)
In-Reply-To: <20221201215651.152497-1-marex@denx.de>
The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to find
out how it works. No functional change.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
V2: Add RB from Peng
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++----
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++---
4 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 423cb36cbcd53..513c2de0caa15 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -563,15 +563,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mm_uid: unique-id@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 312e3abc35ea8..068f599cdf757 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -564,15 +564,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mn_uid: unique-id@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9459ed21b243..ddcd5e23ba47d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -426,19 +426,32 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mp_uid: unique-id@8 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x8 0x8> describes fuses 0x420 and
+ * 0x430).
+ */
+ imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- eth_mac1: mac-address@90 {
+ eth_mac1: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
- eth_mac2: mac-address@96 {
+ eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2b6d3f4ff5d93..8a2ec90b493d9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -593,15 +593,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
- imx8mq_uid: soc-uid@4 {
+ /*
+ * The register address below maps to the MX8M
+ * Fusemap Description Table entries this way.
+ * Assuming
+ * reg = <ADDR SIZE>;
+ * then
+ * Fuse Address = (ADDR * 4) + 0x400
+ * Note that if SIZE is greater than 4, then
+ * each subsequent fuse is located at offset
+ * +0x10 in Fusemap Description Table (e.g.
+ * reg = <0x4 0x8> describes fuses 0x410 and
+ * 0x420).
+ */
+ imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
- cpu_speed_grade: speed-grade@10 {
+ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
- fec_mac_address: mac-address@90 {
+ fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-12-01 21:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 21:56 [PATCH v2 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-01 21:56 ` [PATCH v2 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-01 21:56 ` Marek Vasut [this message]
2022-12-01 21:56 ` [PATCH v2 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut
2022-12-01 21:56 ` [PATCH v2 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-01 21:56 ` [PATCH v2 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-02 8:00 ` kernel test robot
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