From: Marek Vasut <marex@denx.de>
To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>, Peng Fan <peng.fan@nxp.com>,
Adam Ford <aford173@gmail.com>, Alice Guo <alice.guo@nxp.com>,
Amit Kucheria <amitk@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Jun <jun.li@nxp.com>, Lucas Stach <l.stach@pengutronix.de>,
Markus Niebel <Markus.Niebel@ew.tq-group.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Zhang Rui <rui.zhang@intel.com>,
devicetree@vger.kernel.org
Subject: [PATCH v2 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
Date: Thu, 1 Dec 2022 22:56:50 +0100 [thread overview]
Message-ID: <20221201215651.152497-4-marex@denx.de> (raw)
In-Reply-To: <20221201215651.152497-1-marex@denx.de>
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
V2: Add RB from Peng
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 513c2de0caa15..0cd7fff47c44d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -496,6 +496,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 068f599cdf757..5eef9b274edde 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -498,6 +498,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index ddcd5e23ba47d..0173e394ad4d8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -380,6 +380,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
@@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */
eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
+
+ tmu_calib: calib@264 { /* 0xd90-0xdc0 */
+ reg = <0x264 0x10>;
+ };
};
anatop: clock-controller@30360000 {
--
2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Marek Vasut <marex@denx.de>
To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>, Peng Fan <peng.fan@nxp.com>,
Adam Ford <aford173@gmail.com>, Alice Guo <alice.guo@nxp.com>,
Amit Kucheria <amitk@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Jun <jun.li@nxp.com>, Lucas Stach <l.stach@pengutronix.de>,
Markus Niebel <Markus.Niebel@ew.tq-group.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Richard Cochran <richardcochran@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>, Zhang Rui <rui.zhang@intel.com>,
devicetree@vger.kernel.org
Subject: [PATCH v2 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP
Date: Thu, 1 Dec 2022 22:56:50 +0100 [thread overview]
Message-ID: <20221201215651.152497-4-marex@denx.de> (raw)
In-Reply-To: <20221201215651.152497-1-marex@denx.de>
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.
The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Alice Guo <alice.guo@nxp.com>
Cc: Amit Kucheria <amitk@kernel.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: devicetree@vger.kernel.org
To: linux-pm@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
---
V2: Add RB from Peng
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 513c2de0caa15..0cd7fff47c44d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -496,6 +496,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 068f599cdf757..5eef9b274edde 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -498,6 +498,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
+ tmu_calib: calib@3c { /* 0x4f0 */
+ reg = <0x3c 4>;
+ };
+
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index ddcd5e23ba47d..0173e394ad4d8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -380,6 +380,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
+ nvmem-cells = <&tmu_calib>;
+ nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
@@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */
eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
+
+ tmu_calib: calib@264 { /* 0xd90-0xdc0 */
+ reg = <0x264 0x10>;
+ };
};
anatop: clock-controller@30360000 {
--
2.35.1
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next prev parent reply other threads:[~2022-12-01 21:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 21:56 [PATCH v2 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-01 21:56 ` [PATCH v2 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-01 21:56 ` [PATCH v2 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-01 21:56 ` Marek Vasut [this message]
2022-12-01 21:56 ` [PATCH v2 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut
2022-12-01 21:56 ` [PATCH v2 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut
2022-12-01 21:56 ` Marek Vasut
2022-12-02 8:00 ` kernel test robot
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