From: Conor Dooley <conor@kernel.org> To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com Cc: Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 7/9] RISC-V: create a function based cache management interface Date: Tue, 3 Jan 2023 21:03:59 +0000 [thread overview] Message-ID: <20230103210400.3500626-8-conor@kernel.org> (raw) In-Reply-To: <Y62nOqzyuUKqYDpq@spud> From: Conor Dooley <conor.dooley@microchip.com> The Zicbo* set of extensions for cache maintenance arrived too late & several SoCs exist without them that require non-coherent DMA. As things stand, the StarFive JH7100, Microchip PolarFire SoC & Renesas RZ/Five all require cache maintenance and lack instructions for this purpose. Similar to the interface already used by the SiFive CCache driver to add cacheinfo_ops, create an interface for registering cache management functions for a given cache controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Yes, I made the cmo_patchfunc() __maybe_unused to escape LKP complaints. The other option that Prabhakar mentioned was having explicit functions for each of the operations, in which case I cmo_patchfunc() would go away. I don't particularly like the name of that function, so any suggestions there would be great! --- arch/riscv/Kconfig.erratas | 4 ++++ arch/riscv/include/asm/cacheflush.h | 19 +++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 21 +++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index f0f0c1abd52b..b8542e6e8f18 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,5 +1,8 @@ menu "CPU errata selection" +config ERRATA_CMO_FUNC + bool + config ERRATA_ANDES bool "Andes AX45MP errata" depends on !XIP_KERNEL @@ -14,6 +17,7 @@ config ERRATA_ANDES config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select ERRATA_CMO_FUNC select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index e22019668b9e..795205ec2028 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -62,6 +62,25 @@ void riscv_noncoherent_supported(void); static inline void riscv_noncoherent_supported(void) {} #endif +struct riscv_cache_maint_ops { + void (*cmo_patchfunc) (unsigned int cache_size, void *vaddr, + size_t size, int dir, int ops); +}; + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops); +#else +static void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops) {} +#endif + +#ifdef CONFIG_ERRATA_CMO_FUNC +asmlinkage void cmo_patchfunc(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops); +#else +__maybe_unused static void cmo_patchfunc(unsigned int cache_size, void *vaddr, + size_t size, int dir, int ops) {} +#endif + /* * Bits in sys_riscv_flush_icache()'s flags argument. */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index e2b82034f504..2f4f147ea0b9 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -83,3 +83,24 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +static struct riscv_cache_maint_ops *rv_cache_maint_ops; +static DEFINE_STATIC_KEY_FALSE(cmo_patchfunc_present); + +void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops) +{ + rv_cache_maint_ops = ops; + static_branch_enable(&cmo_patchfunc_present); +} +EXPORT_SYMBOL_GPL(riscv_set_cache_maint_ops); + +#ifdef CONFIG_ERRATA_CMO_FUNC +asmlinkage void cmo_patchfunc(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops) +{ + if (!static_branch_unlikely(&cmo_patchfunc_present)) + return; + + rv_cache_maint_ops->cmo_patchfunc(cache_size, vaddr, size, dir, ops); +} +#endif -- 2.39.0
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: conor@kernel.org, arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com Cc: Conor Dooley <conor.dooley@microchip.com>, ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org Subject: [RFC v5.1 7/9] RISC-V: create a function based cache management interface Date: Tue, 3 Jan 2023 21:03:59 +0000 [thread overview] Message-ID: <20230103210400.3500626-8-conor@kernel.org> (raw) In-Reply-To: <Y62nOqzyuUKqYDpq@spud> From: Conor Dooley <conor.dooley@microchip.com> The Zicbo* set of extensions for cache maintenance arrived too late & several SoCs exist without them that require non-coherent DMA. As things stand, the StarFive JH7100, Microchip PolarFire SoC & Renesas RZ/Five all require cache maintenance and lack instructions for this purpose. Similar to the interface already used by the SiFive CCache driver to add cacheinfo_ops, create an interface for registering cache management functions for a given cache controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Yes, I made the cmo_patchfunc() __maybe_unused to escape LKP complaints. The other option that Prabhakar mentioned was having explicit functions for each of the operations, in which case I cmo_patchfunc() would go away. I don't particularly like the name of that function, so any suggestions there would be great! --- arch/riscv/Kconfig.erratas | 4 ++++ arch/riscv/include/asm/cacheflush.h | 19 +++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 21 +++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index f0f0c1abd52b..b8542e6e8f18 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,5 +1,8 @@ menu "CPU errata selection" +config ERRATA_CMO_FUNC + bool + config ERRATA_ANDES bool "Andes AX45MP errata" depends on !XIP_KERNEL @@ -14,6 +17,7 @@ config ERRATA_ANDES config ERRATA_ANDES_CMO bool "Apply Andes cache management errata" depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select ERRATA_CMO_FUNC select RISCV_DMA_NONCOHERENT default y help diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index e22019668b9e..795205ec2028 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -62,6 +62,25 @@ void riscv_noncoherent_supported(void); static inline void riscv_noncoherent_supported(void) {} #endif +struct riscv_cache_maint_ops { + void (*cmo_patchfunc) (unsigned int cache_size, void *vaddr, + size_t size, int dir, int ops); +}; + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops); +#else +static void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops) {} +#endif + +#ifdef CONFIG_ERRATA_CMO_FUNC +asmlinkage void cmo_patchfunc(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops); +#else +__maybe_unused static void cmo_patchfunc(unsigned int cache_size, void *vaddr, + size_t size, int dir, int ops) {} +#endif + /* * Bits in sys_riscv_flush_icache()'s flags argument. */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index e2b82034f504..2f4f147ea0b9 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -83,3 +83,24 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +static struct riscv_cache_maint_ops *rv_cache_maint_ops; +static DEFINE_STATIC_KEY_FALSE(cmo_patchfunc_present); + +void riscv_set_cache_maint_ops(struct riscv_cache_maint_ops *ops) +{ + rv_cache_maint_ops = ops; + static_branch_enable(&cmo_patchfunc_present); +} +EXPORT_SYMBOL_GPL(riscv_set_cache_maint_ops); + +#ifdef CONFIG_ERRATA_CMO_FUNC +asmlinkage void cmo_patchfunc(unsigned int cache_size, void *vaddr, size_t size, + int dir, int ops) +{ + if (!static_branch_unlikely(&cmo_patchfunc_present)) + return; + + rv_cache_maint_ops->cmo_patchfunc(cache_size, vaddr, size, dir, ops); +} +#endif -- 2.39.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-03 21:04 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar 2022-12-12 11:54 ` Prabhakar 2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 12:32 ` Heiko Stuebner 2022-12-12 12:32 ` Heiko Stuebner 2022-12-13 17:21 ` Geert Uytterhoeven 2022-12-13 17:21 ` Geert Uytterhoeven 2022-12-13 17:49 ` Lad, Prabhakar 2022-12-13 17:49 ` Lad, Prabhakar 2022-12-14 14:34 ` Andrew Jones 2022-12-14 14:34 ` Andrew Jones 2022-12-17 21:41 ` Conor Dooley 2022-12-17 21:41 ` Conor Dooley 2022-12-19 11:15 ` Lad, Prabhakar 2022-12-19 11:15 ` Lad, Prabhakar 2022-12-19 16:22 ` Conor Dooley 2022-12-19 16:22 ` Conor Dooley 2022-12-19 16:24 ` Lad, Prabhakar 2022-12-19 16:24 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-17 21:19 ` Conor Dooley 2022-12-17 21:19 ` Conor Dooley 2022-12-19 11:19 ` Lad, Prabhakar 2022-12-19 11:19 ` Lad, Prabhakar 2022-12-19 16:20 ` Conor Dooley 2022-12-19 16:20 ` Conor Dooley 2022-12-21 0:31 ` Lad, Prabhakar 2022-12-21 0:31 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-13 17:14 ` Geert Uytterhoeven 2022-12-13 17:14 ` Geert Uytterhoeven 2022-12-13 17:57 ` Lad, Prabhakar 2022-12-13 17:57 ` Lad, Prabhakar 2022-12-17 20:52 ` Conor Dooley 2022-12-17 20:52 ` Conor Dooley 2022-12-19 11:21 ` Lad, Prabhakar 2022-12-19 11:21 ` Lad, Prabhakar 2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-12 17:28 ` Rob Herring 2022-12-12 17:28 ` Rob Herring 2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar 2022-12-12 11:55 ` Prabhakar 2022-12-15 10:34 ` Geert Uytterhoeven 2022-12-15 10:34 ` Geert Uytterhoeven 2022-12-15 11:03 ` Lad, Prabhakar 2022-12-15 11:03 ` Lad, Prabhakar 2022-12-15 11:10 ` Geert Uytterhoeven 2022-12-15 11:10 ` Geert Uytterhoeven 2022-12-15 17:46 ` Lad, Prabhakar 2022-12-15 17:46 ` Lad, Prabhakar 2022-12-15 19:54 ` Conor Dooley 2022-12-15 19:54 ` Conor Dooley 2022-12-15 20:17 ` Geert Uytterhoeven 2022-12-15 20:17 ` Geert Uytterhoeven 2022-12-15 20:32 ` Conor Dooley 2022-12-15 20:32 ` Conor Dooley 2022-12-15 21:40 ` Palmer Dabbelt 2022-12-15 21:40 ` Palmer Dabbelt 2022-12-16 7:02 ` Christoph Hellwig 2022-12-16 7:02 ` Christoph Hellwig 2022-12-16 16:32 ` Palmer Dabbelt 2022-12-16 16:32 ` Palmer Dabbelt 2022-12-16 20:04 ` Arnd Bergmann 2022-12-16 20:04 ` Arnd Bergmann 2022-12-17 22:52 ` Conor Dooley 2022-12-17 22:52 ` Conor Dooley 2022-12-19 12:43 ` Lad, Prabhakar 2022-12-19 12:43 ` Lad, Prabhakar 2022-12-19 16:08 ` Conor Dooley 2022-12-19 16:08 ` Conor Dooley 2022-12-29 14:05 ` Arnd Bergmann 2022-12-29 14:05 ` Arnd Bergmann 2022-12-29 14:42 ` Conor Dooley 2022-12-29 14:42 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-03 21:03 ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley 2023-01-03 21:03 ` Conor Dooley 2023-01-04 9:50 ` Ben Dooks 2023-01-04 9:50 ` Ben Dooks 2023-01-04 10:18 ` Conor Dooley 2023-01-04 10:18 ` Conor Dooley 2023-01-03 21:03 ` Conor Dooley [this message] 2023-01-03 21:03 ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley 2023-01-03 21:04 ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley 2023-01-03 21:04 ` Conor Dooley 2023-01-03 21:04 ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley 2023-01-03 21:04 ` Conor Dooley 2023-01-03 21:25 ` Palmer Dabbelt 2023-01-03 21:25 ` Palmer Dabbelt 2023-01-03 21:28 ` Arnd Bergmann 2023-01-03 21:28 ` Arnd Bergmann 2023-01-04 0:00 ` Conor Dooley 2023-01-04 0:00 ` Conor Dooley 2023-01-04 8:17 ` Arnd Bergmann 2023-01-04 8:17 ` Arnd Bergmann 2023-01-04 9:23 ` Conor Dooley 2023-01-04 9:23 ` Conor Dooley 2023-01-04 10:19 ` Arnd Bergmann 2023-01-04 10:19 ` Arnd Bergmann 2023-01-04 11:56 ` Conor Dooley 2023-01-04 11:56 ` Conor Dooley 2023-01-04 12:18 ` Arnd Bergmann 2023-01-04 12:18 ` Arnd Bergmann 2023-01-04 13:20 ` Conor Dooley 2023-01-04 13:20 ` Conor Dooley 2023-01-04 14:15 ` Arnd Bergmann 2023-01-04 14:15 ` Arnd Bergmann 2023-01-04 9:45 ` Ben Dooks 2023-01-04 9:45 ` Ben Dooks 2023-01-04 9:57 ` Conor Dooley 2023-01-04 9:57 ` Conor Dooley 2022-12-17 21:35 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley 2022-12-17 21:35 ` Conor Dooley 2022-12-28 3:16 ` Samuel Holland 2022-12-28 3:16 ` Samuel Holland
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