From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Samuel Holland <samuel@sholland.org>, Guo Ren <guoren@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP()
Date: Tue, 13 Dec 2022 18:14:55 +0100 [thread overview]
Message-ID: <CAMuHMdXeeCoHNt0tSD51HmexQG7qVBnJO+-_pURix7fr678LNQ@mail.gmail.com> (raw)
In-Reply-To: <20221212115505.36770-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Mon, Dec 12, 2022 at 12:55 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Pass direction and operation to ALT_CMO_OP() macro.
>
> Vendors might want to perform different operations based on the direction
> and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/
> arch_dma_prep_coherent) so to handle such cases pass the direction and
> operation to ALT_CMO_OP() macro. This is in preparation for adding errata
> for the Andes CPU core.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
> +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
Since commit a49ab905a1fc8630 ("RISC-V: Implement arch specific PMEM
APIs") in riscv/for-next, there are two new users of this macro,
which need to be updated to (add two zeroes?).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Samuel Holland <samuel@sholland.org>,
Guo Ren <guoren@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Jisheng Zhang <jszhang@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Nathan Chancellor <nathan@kernel.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP()
Date: Tue, 13 Dec 2022 18:14:55 +0100 [thread overview]
Message-ID: <CAMuHMdXeeCoHNt0tSD51HmexQG7qVBnJO+-_pURix7fr678LNQ@mail.gmail.com> (raw)
In-Reply-To: <20221212115505.36770-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Mon, Dec 12, 2022 at 12:55 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Pass direction and operation to ALT_CMO_OP() macro.
>
> Vendors might want to perform different operations based on the direction
> and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/
> arch_dma_prep_coherent) so to handle such cases pass the direction and
> operation to ALT_CMO_OP() macro. This is in preparation for adding errata
> for the Andes CPU core.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
> +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \
Since commit a49ab905a1fc8630 ("RISC-V: Implement arch specific PMEM
APIs") in riscv/for-next, there are two new users of this macro,
which need to be updated to (add two zeroes?).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-13 17:15 UTC|newest]
Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-12 11:54 [PATCH v5 0/6] AX45MP: Add support to non-coherent DMA Prabhakar
2022-12-12 11:54 ` Prabhakar
2022-12-12 11:55 ` [PATCH v5 1/6] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Prabhakar
2022-12-12 11:55 ` Prabhakar
2022-12-12 12:32 ` Heiko Stuebner
2022-12-12 12:32 ` Heiko Stuebner
2022-12-13 17:21 ` Geert Uytterhoeven
2022-12-13 17:21 ` Geert Uytterhoeven
2022-12-13 17:49 ` Lad, Prabhakar
2022-12-13 17:49 ` Lad, Prabhakar
2022-12-14 14:34 ` Andrew Jones
2022-12-14 14:34 ` Andrew Jones
2022-12-17 21:41 ` Conor Dooley
2022-12-17 21:41 ` Conor Dooley
2022-12-19 11:15 ` Lad, Prabhakar
2022-12-19 11:15 ` Lad, Prabhakar
2022-12-19 16:22 ` Conor Dooley
2022-12-19 16:22 ` Conor Dooley
2022-12-19 16:24 ` Lad, Prabhakar
2022-12-19 16:24 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2022-12-12 11:55 ` Prabhakar
2022-12-12 11:55 ` [PATCH v5 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2022-12-12 11:55 ` Prabhakar
2022-12-17 21:19 ` Conor Dooley
2022-12-17 21:19 ` Conor Dooley
2022-12-19 11:19 ` Lad, Prabhakar
2022-12-19 11:19 ` Lad, Prabhakar
2022-12-19 16:20 ` Conor Dooley
2022-12-19 16:20 ` Conor Dooley
2022-12-21 0:31 ` Lad, Prabhakar
2022-12-21 0:31 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Prabhakar
2022-12-12 11:55 ` Prabhakar
2022-12-13 17:14 ` Geert Uytterhoeven [this message]
2022-12-13 17:14 ` Geert Uytterhoeven
2022-12-13 17:57 ` Lad, Prabhakar
2022-12-13 17:57 ` Lad, Prabhakar
2022-12-17 20:52 ` Conor Dooley
2022-12-17 20:52 ` Conor Dooley
2022-12-19 11:21 ` Lad, Prabhakar
2022-12-19 11:21 ` Lad, Prabhakar
2022-12-12 11:55 ` [PATCH v5 5/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-12-12 11:55 ` Prabhakar
2022-12-12 17:28 ` Rob Herring
2022-12-12 17:28 ` Rob Herring
2022-12-12 11:55 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-12-12 11:55 ` Prabhakar
2022-12-15 10:34 ` Geert Uytterhoeven
2022-12-15 10:34 ` Geert Uytterhoeven
2022-12-15 11:03 ` Lad, Prabhakar
2022-12-15 11:03 ` Lad, Prabhakar
2022-12-15 11:10 ` Geert Uytterhoeven
2022-12-15 11:10 ` Geert Uytterhoeven
2022-12-15 17:46 ` Lad, Prabhakar
2022-12-15 17:46 ` Lad, Prabhakar
2022-12-15 19:54 ` Conor Dooley
2022-12-15 19:54 ` Conor Dooley
2022-12-15 20:17 ` Geert Uytterhoeven
2022-12-15 20:17 ` Geert Uytterhoeven
2022-12-15 20:32 ` Conor Dooley
2022-12-15 20:32 ` Conor Dooley
2022-12-15 21:40 ` Palmer Dabbelt
2022-12-15 21:40 ` Palmer Dabbelt
2022-12-16 7:02 ` Christoph Hellwig
2022-12-16 7:02 ` Christoph Hellwig
2022-12-16 16:32 ` Palmer Dabbelt
2022-12-16 16:32 ` Palmer Dabbelt
2022-12-16 20:04 ` Arnd Bergmann
2022-12-16 20:04 ` Arnd Bergmann
2022-12-17 22:52 ` Conor Dooley
2022-12-17 22:52 ` Conor Dooley
2022-12-19 12:43 ` Lad, Prabhakar
2022-12-19 12:43 ` Lad, Prabhakar
2022-12-19 16:08 ` Conor Dooley
2022-12-19 16:08 ` Conor Dooley
2022-12-29 14:05 ` Arnd Bergmann
2022-12-29 14:05 ` Arnd Bergmann
2022-12-29 14:42 ` Conor Dooley
2022-12-29 14:42 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 0/9] Generic function based cache management operations (was Re: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC) Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 1/9] riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 2/9] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 3/9] riscv: errata: Add Andes alternative ports Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 4/9] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 5/9] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-04 9:50 ` Ben Dooks
2023-01-04 9:50 ` Ben Dooks
2023-01-04 10:18 ` Conor Dooley
2023-01-04 10:18 ` Conor Dooley
2023-01-03 21:03 ` [RFC v5.1 7/9] RISC-V: create a function based cache management interface Conor Dooley
2023-01-03 21:03 ` Conor Dooley
2023-01-03 21:04 ` [RFC v5.1 8/9] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2023-01-03 21:04 ` Conor Dooley
2023-01-03 21:04 ` [RFC v5.1 9/9] [DON'T APPLY] cache: sifive-ccache: add cache flushing capability Conor Dooley
2023-01-03 21:04 ` Conor Dooley
2023-01-03 21:25 ` Palmer Dabbelt
2023-01-03 21:25 ` Palmer Dabbelt
2023-01-03 21:28 ` Arnd Bergmann
2023-01-03 21:28 ` Arnd Bergmann
2023-01-04 0:00 ` Conor Dooley
2023-01-04 0:00 ` Conor Dooley
2023-01-04 8:17 ` Arnd Bergmann
2023-01-04 8:17 ` Arnd Bergmann
2023-01-04 9:23 ` Conor Dooley
2023-01-04 9:23 ` Conor Dooley
2023-01-04 10:19 ` Arnd Bergmann
2023-01-04 10:19 ` Arnd Bergmann
2023-01-04 11:56 ` Conor Dooley
2023-01-04 11:56 ` Conor Dooley
2023-01-04 12:18 ` Arnd Bergmann
2023-01-04 12:18 ` Arnd Bergmann
2023-01-04 13:20 ` Conor Dooley
2023-01-04 13:20 ` Conor Dooley
2023-01-04 14:15 ` Arnd Bergmann
2023-01-04 14:15 ` Arnd Bergmann
2023-01-04 9:45 ` Ben Dooks
2023-01-04 9:45 ` Ben Dooks
2023-01-04 9:57 ` Conor Dooley
2023-01-04 9:57 ` Conor Dooley
2022-12-17 21:35 ` [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC Conor Dooley
2022-12-17 21:35 ` Conor Dooley
2022-12-28 3:16 ` Samuel Holland
2022-12-28 3:16 ` Samuel Holland
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