From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, "Emil Renner Berthing" <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v6 09/11] riscv: dts: starfive: jh7110: add pmu controller node Date: Thu, 18 May 2023 18:12:32 +0800 [thread overview] Message-ID: <20230518101234.143748-10-xingyu.wu@starfivetech.com> (raw) In-Reply-To: <20230518101234.143748-1-xingyu.wu@starfivetech.com> From: Walker Chen <walker.chen@starfivetech.com> Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs to be used by other modules such as VPU, ISP, etc. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..30e1f34d5cf8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -496,5 +496,12 @@ aongpio: pinctrl@17020000 { gpio-controller; #gpio-cells = <2>; }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; }; }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Xingyu Wu <xingyu.wu@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Philipp Zabel <p.zabel@pengutronix.de>, Conor Dooley <conor@kernel.org>, "Emil Renner Berthing" <kernel@esmil.dk> Cc: Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, Xingyu Wu <xingyu.wu@starfivetech.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org> Subject: [PATCH v6 09/11] riscv: dts: starfive: jh7110: add pmu controller node Date: Thu, 18 May 2023 18:12:32 +0800 [thread overview] Message-ID: <20230518101234.143748-10-xingyu.wu@starfivetech.com> (raw) In-Reply-To: <20230518101234.143748-1-xingyu.wu@starfivetech.com> From: Walker Chen <walker.chen@starfivetech.com> Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs to be used by other modules such as VPU, ISP, etc. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..30e1f34d5cf8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -496,5 +496,12 @@ aongpio: pinctrl@17020000 { gpio-controller; #gpio-cells = <2>; }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; }; }; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-05-18 10:13 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-18 10:12 [PATCH v6 00/11] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 02/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-31 8:56 ` Hal Feng 2023-05-31 8:56 ` Hal Feng 2023-05-18 10:12 ` [PATCH v6 03/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 04/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 05/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 06/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 07/11] MAINTAINERS: Update maintainer of JH71x0 clock drivers Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-18 10:12 ` [PATCH v6 08/11] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-31 8:36 ` Hal Feng 2023-05-31 8:36 ` Hal Feng 2023-05-18 10:12 ` Xingyu Wu [this message] 2023-05-18 10:12 ` [PATCH v6 09/11] riscv: dts: starfive: jh7110: add pmu controller node Xingyu Wu 2023-05-25 21:42 ` Conor Dooley 2023-05-25 21:42 ` Conor Dooley 2023-05-18 10:12 ` [PATCH v6 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-05-25 21:44 ` Conor Dooley 2023-05-25 21:44 ` Conor Dooley 2023-05-18 10:12 ` [PATCH v6 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu 2023-05-18 10:12 ` Xingyu Wu 2023-07-01 15:45 ` [PATCH v6 00/11] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 patchwork-bot+linux-riscv 2023-07-01 15:45 ` patchwork-bot+linux-riscv
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