From: Jisheng Zhang <jszhang@kernel.org> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Date: Sun, 18 Jun 2023 00:15:21 +0800 [thread overview] Message-ID: <20230617161529.2092-1-jszhang@kernel.org> (raw) Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. NOTE: the thead cpu reset dt-binding and DT node are removed in v3. This makes secondary CPUs unable to be online. However, minimal th1520 support is better than nothing. And the community has been working on and will work on the cpu reset dt-binding, for example, Conor, Guo and Jessica are discussing about it, I have seen valuable comments and inputs from them. I believe we can add back cpu reset in next development window. Thanks Since v2: - remove thead cpu-rst dt-binding doc and its DT node from th1520.dtsi - collect Reviewed-by and Acked-by tags - update uart reg size as suggested by Yixun - Add Guo Ren and Fu Wei as THEAD SoCs Maintainers Since v1: - add missing plic, clint, th1520 itself dt-bindings - use c900-plic - s/light/th1520 - add dt-binding for T-HEAD CPU reset - enable ARCH_THEAD in defconfig - fix all dtbs_check error/warning except the CPU RESET, see above. Jisheng Zhang (8): dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC dt-bindings: timer: Add T-HEAD TH1520 clint dt-bindings: riscv: Add T-HEAD TH1520 board compatibles riscv: Add the T-HEAD SoC family Kconfig option riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: dts: thead: add sipeed Lichee Pi 4A board device tree MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: defconfig: enable T-HEAD SoC .../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/thead.yaml | 29 ++ .../bindings/timer/sifive,clint.yaml | 1 + MAINTAINERS | 8 + arch/riscv/Kconfig.socs | 6 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 ++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/boot/dts/thead/th1520.dtsi | 422 ++++++++++++++++++ arch/riscv/configs/defconfig | 1 + 11 files changed, 541 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi -- 2.40.0
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Date: Sun, 18 Jun 2023 00:15:21 +0800 [thread overview] Message-ID: <20230617161529.2092-1-jszhang@kernel.org> (raw) Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. NOTE: the thead cpu reset dt-binding and DT node are removed in v3. This makes secondary CPUs unable to be online. However, minimal th1520 support is better than nothing. And the community has been working on and will work on the cpu reset dt-binding, for example, Conor, Guo and Jessica are discussing about it, I have seen valuable comments and inputs from them. I believe we can add back cpu reset in next development window. Thanks Since v2: - remove thead cpu-rst dt-binding doc and its DT node from th1520.dtsi - collect Reviewed-by and Acked-by tags - update uart reg size as suggested by Yixun - Add Guo Ren and Fu Wei as THEAD SoCs Maintainers Since v1: - add missing plic, clint, th1520 itself dt-bindings - use c900-plic - s/light/th1520 - add dt-binding for T-HEAD CPU reset - enable ARCH_THEAD in defconfig - fix all dtbs_check error/warning except the CPU RESET, see above. Jisheng Zhang (8): dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC dt-bindings: timer: Add T-HEAD TH1520 clint dt-bindings: riscv: Add T-HEAD TH1520 board compatibles riscv: Add the T-HEAD SoC family Kconfig option riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: dts: thead: add sipeed Lichee Pi 4A board device tree MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: defconfig: enable T-HEAD SoC .../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/thead.yaml | 29 ++ .../bindings/timer/sifive,clint.yaml | 1 + MAINTAINERS | 8 + arch/riscv/Kconfig.socs | 6 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 ++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++ arch/riscv/boot/dts/thead/th1520.dtsi | 422 ++++++++++++++++++ arch/riscv/configs/defconfig | 1 + 11 files changed, 541 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi -- 2.40.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2023-06-17 16:26 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-17 16:15 Jisheng Zhang [this message] 2023-06-17 16:15 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley 2023-06-17 17:02 ` Conor Dooley 2023-06-18 16:14 ` Jisheng Zhang 2023-06-18 16:14 ` Jisheng Zhang 2023-06-17 18:20 ` Conor Dooley 2023-06-17 18:20 ` Conor Dooley 2023-06-18 16:25 ` Jisheng Zhang 2023-06-18 16:25 ` Jisheng Zhang 2023-06-18 21:01 ` Conor Dooley 2023-06-18 21:01 ` Conor Dooley 2023-06-20 22:52 ` Conor Dooley 2023-06-20 22:52 ` Conor Dooley 2023-06-20 22:55 ` Conor Dooley 2023-06-20 22:55 ` Conor Dooley 2023-07-25 7:38 ` Xi Ruoyao 2023-07-25 7:38 ` Xi Ruoyao 2023-07-25 7:52 ` Conor Dooley 2023-07-25 7:52 ` Conor Dooley 2023-07-25 8:10 ` Conor Dooley 2023-07-25 8:10 ` Conor Dooley 2023-07-25 14:32 ` Drew Fustini 2023-07-25 14:32 ` Drew Fustini 2023-07-25 8:26 ` Xi Ruoyao 2023-07-25 8:26 ` Xi Ruoyao 2023-07-25 14:58 ` Jisheng Zhang 2023-07-25 14:58 ` Jisheng Zhang 2023-07-26 12:48 ` Xi Ruoyao 2023-07-26 12:48 ` Xi Ruoyao 2023-07-26 15:00 ` Jisheng Zhang 2023-07-26 15:00 ` Jisheng Zhang 2023-07-27 0:14 ` Xi Ruoyao 2023-07-27 0:14 ` Xi Ruoyao 2023-07-27 0:54 ` Xi Ruoyao 2023-07-27 0:54 ` Xi Ruoyao 2023-07-27 9:18 ` Xi Ruoyao 2023-07-27 9:18 ` Xi Ruoyao 2023-07-27 16:11 ` Jisheng Zhang 2023-07-27 16:11 ` Jisheng Zhang 2023-07-27 16:29 ` Xi Ruoyao 2023-07-27 16:29 ` Xi Ruoyao 2023-07-28 7:04 ` Drew Fustini 2023-07-28 7:04 ` Drew Fustini 2023-07-28 7:40 ` Xi Ruoyao 2023-07-28 7:40 ` Xi Ruoyao 2023-07-28 10:05 ` Xi Ruoyao 2023-07-28 10:05 ` Xi Ruoyao 2023-07-28 10:23 ` Emil Renner Berthing 2023-07-28 10:23 ` Emil Renner Berthing 2023-07-28 17:53 ` Drew Fustini 2023-07-28 17:53 ` Drew Fustini 2023-07-29 7:11 ` Xi Ruoyao 2023-07-29 7:11 ` Xi Ruoyao 2023-07-28 0:11 ` Drew Fustini 2023-07-28 0:11 ` Drew Fustini 2023-08-11 17:39 ` Drew Fustini 2023-08-11 17:39 ` Drew Fustini 2023-08-11 17:46 ` Conor Dooley 2023-08-11 17:46 ` Conor Dooley
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