From: Jisheng Zhang <jszhang@kernel.org> To: Conor Dooley <conor@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, arnd@arndb.de Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Date: Mon, 19 Jun 2023 00:25:54 +0800 [thread overview] Message-ID: <ZI8wEp52bpqaCHAl@xhacker> (raw) In-Reply-To: <20230617-duress-phantom-3da79e33f204@spud> On Sat, Jun 17, 2023 at 07:20:43PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > On Sun, 18 Jun 2023 00:15:21 +0800, Jisheng Zhang wrote: > > Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core > > module which is powered by T-HEAD's TH1520 SoC. Add minimal device > > tree files for the core module and the development board. > > > > Support basic uart/gpio/dmac drivers, so supports booting to a basic > > shell. > > > > [...] > > Applied to riscv-dt-for-next, thanks! > > [1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC > https://git.kernel.org/conor/c/a04cc7391d88 > [2/8] dt-bindings: timer: Add T-HEAD TH1520 clint > https://git.kernel.org/conor/c/413c24b03f4e > [3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles > https://git.kernel.org/conor/c/89b0186ab532 > [4/8] riscv: Add the T-HEAD SoC family Kconfig option > https://git.kernel.org/conor/c/da47ce003963 > [5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree > https://git.kernel.org/conor/c/8e396880a864 > [6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree > https://git.kernel.org/conor/c/5af4cb0c42c5 > [7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC > https://git.kernel.org/conor/c/1203f584fe66 > [8/8] riscv: defconfig: enable T-HEAD SoC > https://git.kernel.org/conor/c/318afa081204 > > I'll send it to Arnd as a "RISC-V Devicetrees for v6.5 Part 2" once it > has been in linux-next for a day or two. Thank you so much for helping the PR this time. > > Going forward, who is going to pick up the patches and send the PRs to > Arnd? I wrote a document that should be in v6.5 about SoC tree Here is what I thought: From next development window, If we see a heavy development window, IOW, the patches size is big, I will take the job of picking up patches and sending out PRs. Once the development calms down, the patches size is trivial, I will explictly send request to you by repling the patches to ask your help to directly take the patches and send PRs. Any comments are appreciated. Thanks > submaintainer stuff that is worth reading: > https://lore.kernel.org/all/20230606-escapable-stuffed-7ca5033e7741@wendy/ The handbook is a wonderful document, thank you! > > I'll do it if nobody else is willing to, but I don't want to be > responsible for applying patches for all the platforms that pop up, > especially for ones that I don't even have the hardware for ;) > > Thanks, > Conor.
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: Conor Dooley <conor@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, arnd@arndb.de Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Date: Mon, 19 Jun 2023 00:25:54 +0800 [thread overview] Message-ID: <ZI8wEp52bpqaCHAl@xhacker> (raw) In-Reply-To: <20230617-duress-phantom-3da79e33f204@spud> On Sat, Jun 17, 2023 at 07:20:43PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > On Sun, 18 Jun 2023 00:15:21 +0800, Jisheng Zhang wrote: > > Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core > > module which is powered by T-HEAD's TH1520 SoC. Add minimal device > > tree files for the core module and the development board. > > > > Support basic uart/gpio/dmac drivers, so supports booting to a basic > > shell. > > > > [...] > > Applied to riscv-dt-for-next, thanks! > > [1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC > https://git.kernel.org/conor/c/a04cc7391d88 > [2/8] dt-bindings: timer: Add T-HEAD TH1520 clint > https://git.kernel.org/conor/c/413c24b03f4e > [3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles > https://git.kernel.org/conor/c/89b0186ab532 > [4/8] riscv: Add the T-HEAD SoC family Kconfig option > https://git.kernel.org/conor/c/da47ce003963 > [5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree > https://git.kernel.org/conor/c/8e396880a864 > [6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree > https://git.kernel.org/conor/c/5af4cb0c42c5 > [7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC > https://git.kernel.org/conor/c/1203f584fe66 > [8/8] riscv: defconfig: enable T-HEAD SoC > https://git.kernel.org/conor/c/318afa081204 > > I'll send it to Arnd as a "RISC-V Devicetrees for v6.5 Part 2" once it > has been in linux-next for a day or two. Thank you so much for helping the PR this time. > > Going forward, who is going to pick up the patches and send the PRs to > Arnd? I wrote a document that should be in v6.5 about SoC tree Here is what I thought: From next development window, If we see a heavy development window, IOW, the patches size is big, I will take the job of picking up patches and sending out PRs. Once the development calms down, the patches size is trivial, I will explictly send request to you by repling the patches to ask your help to directly take the patches and send PRs. Any comments are appreciated. Thanks > submaintainer stuff that is worth reading: > https://lore.kernel.org/all/20230606-escapable-stuffed-7ca5033e7741@wendy/ The handbook is a wonderful document, thank you! > > I'll do it if nobody else is willing to, but I don't want to be > responsible for applying patches for all the platforms that pop up, > especially for ones that I don't even have the hardware for ;) > > Thanks, > Conor. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-06-18 16:37 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang 2023-06-17 16:15 ` Jisheng Zhang 2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley 2023-06-17 17:02 ` Conor Dooley 2023-06-18 16:14 ` Jisheng Zhang 2023-06-18 16:14 ` Jisheng Zhang 2023-06-17 18:20 ` Conor Dooley 2023-06-17 18:20 ` Conor Dooley 2023-06-18 16:25 ` Jisheng Zhang [this message] 2023-06-18 16:25 ` Jisheng Zhang 2023-06-18 21:01 ` Conor Dooley 2023-06-18 21:01 ` Conor Dooley 2023-06-20 22:52 ` Conor Dooley 2023-06-20 22:52 ` Conor Dooley 2023-06-20 22:55 ` Conor Dooley 2023-06-20 22:55 ` Conor Dooley 2023-07-25 7:38 ` Xi Ruoyao 2023-07-25 7:38 ` Xi Ruoyao 2023-07-25 7:52 ` Conor Dooley 2023-07-25 7:52 ` Conor Dooley 2023-07-25 8:10 ` Conor Dooley 2023-07-25 8:10 ` Conor Dooley 2023-07-25 14:32 ` Drew Fustini 2023-07-25 14:32 ` Drew Fustini 2023-07-25 8:26 ` Xi Ruoyao 2023-07-25 8:26 ` Xi Ruoyao 2023-07-25 14:58 ` Jisheng Zhang 2023-07-25 14:58 ` Jisheng Zhang 2023-07-26 12:48 ` Xi Ruoyao 2023-07-26 12:48 ` Xi Ruoyao 2023-07-26 15:00 ` Jisheng Zhang 2023-07-26 15:00 ` Jisheng Zhang 2023-07-27 0:14 ` Xi Ruoyao 2023-07-27 0:14 ` Xi Ruoyao 2023-07-27 0:54 ` Xi Ruoyao 2023-07-27 0:54 ` Xi Ruoyao 2023-07-27 9:18 ` Xi Ruoyao 2023-07-27 9:18 ` Xi Ruoyao 2023-07-27 16:11 ` Jisheng Zhang 2023-07-27 16:11 ` Jisheng Zhang 2023-07-27 16:29 ` Xi Ruoyao 2023-07-27 16:29 ` Xi Ruoyao 2023-07-28 7:04 ` Drew Fustini 2023-07-28 7:04 ` Drew Fustini 2023-07-28 7:40 ` Xi Ruoyao 2023-07-28 7:40 ` Xi Ruoyao 2023-07-28 10:05 ` Xi Ruoyao 2023-07-28 10:05 ` Xi Ruoyao 2023-07-28 10:23 ` Emil Renner Berthing 2023-07-28 10:23 ` Emil Renner Berthing 2023-07-28 17:53 ` Drew Fustini 2023-07-28 17:53 ` Drew Fustini 2023-07-29 7:11 ` Xi Ruoyao 2023-07-29 7:11 ` Xi Ruoyao 2023-07-28 0:11 ` Drew Fustini 2023-07-28 0:11 ` Drew Fustini 2023-08-11 17:39 ` Drew Fustini 2023-08-11 17:39 ` Drew Fustini 2023-08-11 17:46 ` Conor Dooley 2023-08-11 17:46 ` Conor Dooley
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