From: Yang Li <yang.lee@linux.alibaba.com> To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch, harry.wentland@amd.com, Rodrigo.Siqueira@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yang Li <yang.lee@linux.alibaba.com> Subject: [PATCH -next 3/5] drm/amd/display: clean up some inconsistent indentings Date: Fri, 1 Sep 2023 09:29:22 +0800 [thread overview] Message-ID: <20230901012924.120196-3-yang.lee@linux.alibaba.com> (raw) In-Reply-To: <20230901012924.120196-1-yang.lee@linux.alibaba.com> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_hwseq.c:159 dcn35_init_hw() warn: inconsistent indentig Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> --- .../drm/amd/display/dc/dcn35/dcn35_hwseq.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c index 666e2809d9dc..025849143254 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c @@ -155,22 +155,22 @@ void dcn35_init_hw(struct dc *dc) res_pool->ref_clocks.xtalin_clock_inKhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; - if (res_pool->dccg && res_pool->hubbub) { - - (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, - dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, - &res_pool->ref_clocks.dccg_ref_clock_inKhz); - - (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, - res_pool->ref_clocks.dccg_ref_clock_inKhz, - &res_pool->ref_clocks.dchub_ref_clock_inKhz); - } else { - // Not all ASICs have DCCG sw component - res_pool->ref_clocks.dccg_ref_clock_inKhz = - res_pool->ref_clocks.xtalin_clock_inKhz; - res_pool->ref_clocks.dchub_ref_clock_inKhz = - res_pool->ref_clocks.xtalin_clock_inKhz; - } + if (res_pool->dccg && res_pool->hubbub) { + + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } } else ASSERT_CRITICAL(false); -- 2.20.1.7.g153144c
WARNING: multiple messages have this Message-ID (diff)
From: Yang Li <yang.lee@linux.alibaba.com> To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch, harry.wentland@amd.com, Rodrigo.Siqueira@amd.com Cc: Yang Li <yang.lee@linux.alibaba.com>, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH -next 3/5] drm/amd/display: clean up some inconsistent indentings Date: Fri, 1 Sep 2023 09:29:22 +0800 [thread overview] Message-ID: <20230901012924.120196-3-yang.lee@linux.alibaba.com> (raw) In-Reply-To: <20230901012924.120196-1-yang.lee@linux.alibaba.com> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_hwseq.c:159 dcn35_init_hw() warn: inconsistent indentig Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> --- .../drm/amd/display/dc/dcn35/dcn35_hwseq.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c index 666e2809d9dc..025849143254 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c @@ -155,22 +155,22 @@ void dcn35_init_hw(struct dc *dc) res_pool->ref_clocks.xtalin_clock_inKhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; - if (res_pool->dccg && res_pool->hubbub) { - - (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, - dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, - &res_pool->ref_clocks.dccg_ref_clock_inKhz); - - (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, - res_pool->ref_clocks.dccg_ref_clock_inKhz, - &res_pool->ref_clocks.dchub_ref_clock_inKhz); - } else { - // Not all ASICs have DCCG sw component - res_pool->ref_clocks.dccg_ref_clock_inKhz = - res_pool->ref_clocks.xtalin_clock_inKhz; - res_pool->ref_clocks.dchub_ref_clock_inKhz = - res_pool->ref_clocks.xtalin_clock_inKhz; - } + if (res_pool->dccg && res_pool->hubbub) { + + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } } else ASSERT_CRITICAL(false); -- 2.20.1.7.g153144c
next prev parent reply other threads:[~2023-09-01 1:29 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-09-01 1:29 [PATCH -next 1/5] drm/amd/display: clean up one inconsistent indenting Yang Li 2023-09-01 1:29 ` Yang Li 2023-09-01 1:29 ` [PATCH -next 2/5] " Yang Li 2023-09-01 1:29 ` Yang Li 2023-09-01 1:29 ` Yang Li [this message] 2023-09-01 1:29 ` [PATCH -next 3/5] drm/amd/display: clean up some inconsistent indentings Yang Li 2023-09-01 1:29 ` [PATCH -next 4/5] " Yang Li 2023-09-01 1:29 ` Yang Li 2023-09-01 1:29 ` [PATCH -next 5/5] drm/amd/display: clean up one inconsistent indenting Yang Li 2023-09-01 1:29 ` Yang Li 2023-09-05 17:38 ` Alex Deucher 2023-09-05 17:38 ` Alex Deucher 2023-09-05 17:38 ` Alex Deucher
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