From: Yang Li <yang.lee@linux.alibaba.com>
To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch,
harry.wentland@amd.com, Rodrigo.Siqueira@amd.com
Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org,
Yang Li <yang.lee@linux.alibaba.com>
Subject: [PATCH -next 4/5] drm/amd/display: clean up some inconsistent indentings
Date: Fri, 1 Sep 2023 09:29:23 +0800 [thread overview]
Message-ID: <20230901012924.120196-4-yang.lee@linux.alibaba.com> (raw)
In-Reply-To: <20230901012924.120196-1-yang.lee@linux.alibaba.com>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:288 dcn35_update_clocks() warn: inconsistent indenting
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 9314e75195cd..98d6a1f8af60 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -288,8 +288,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
- if (new_clocks->dppclk_khz < 100000)
- new_clocks->dppclk_khz = 100000;
+ if (new_clocks->dppclk_khz < 100000)
+ new_clocks->dppclk_khz = 100000;
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@@ -901,21 +901,21 @@ void dcn35_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
- clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
+ clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
- if (clk_mgr->base.smu_ver)
- clk_mgr->base.smu_present = true;
+ if (clk_mgr->base.smu_ver)
+ clk_mgr->base.smu_present = true;
- /* TODO: Check we get what we expect during bringup */
- clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
+ /* TODO: Check we get what we expect during bringup */
+ clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
- if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
- dcn35_bw_params.wm_table = lpddr5_wm_table;
- } else {
- dcn35_bw_params.wm_table = ddr5_wm_table;
- }
- /* Saved clocks configured at boot for debug purposes */
- dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
+ if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
+ dcn35_bw_params.wm_table = lpddr5_wm_table;
+ } else {
+ dcn35_bw_params.wm_table = ddr5_wm_table;
+ }
+ /* Saved clocks configured at boot for debug purposes */
+ dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
clk_mgr->base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&clk_mgr->base);
--
2.20.1.7.g153144c
WARNING: multiple messages have this Message-ID (diff)
From: Yang Li <yang.lee@linux.alibaba.com>
To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch,
harry.wentland@amd.com, Rodrigo.Siqueira@amd.com
Cc: Yang Li <yang.lee@linux.alibaba.com>,
dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org
Subject: [PATCH -next 4/5] drm/amd/display: clean up some inconsistent indentings
Date: Fri, 1 Sep 2023 09:29:23 +0800 [thread overview]
Message-ID: <20230901012924.120196-4-yang.lee@linux.alibaba.com> (raw)
In-Reply-To: <20230901012924.120196-1-yang.lee@linux.alibaba.com>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:288 dcn35_update_clocks() warn: inconsistent indenting
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 9314e75195cd..98d6a1f8af60 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -288,8 +288,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
- if (new_clocks->dppclk_khz < 100000)
- new_clocks->dppclk_khz = 100000;
+ if (new_clocks->dppclk_khz < 100000)
+ new_clocks->dppclk_khz = 100000;
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
@@ -901,21 +901,21 @@ void dcn35_clk_mgr_construct(
ASSERT(smu_dpm_clks.dpm_clks);
- clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
+ clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
- if (clk_mgr->base.smu_ver)
- clk_mgr->base.smu_present = true;
+ if (clk_mgr->base.smu_ver)
+ clk_mgr->base.smu_present = true;
- /* TODO: Check we get what we expect during bringup */
- clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
+ /* TODO: Check we get what we expect during bringup */
+ clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
- if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
- dcn35_bw_params.wm_table = lpddr5_wm_table;
- } else {
- dcn35_bw_params.wm_table = ddr5_wm_table;
- }
- /* Saved clocks configured at boot for debug purposes */
- dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
+ if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
+ dcn35_bw_params.wm_table = lpddr5_wm_table;
+ } else {
+ dcn35_bw_params.wm_table = ddr5_wm_table;
+ }
+ /* Saved clocks configured at boot for debug purposes */
+ dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
clk_mgr->base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&clk_mgr->base);
--
2.20.1.7.g153144c
next prev parent reply other threads:[~2023-09-01 1:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 1:29 [PATCH -next 1/5] drm/amd/display: clean up one inconsistent indenting Yang Li
2023-09-01 1:29 ` Yang Li
2023-09-01 1:29 ` [PATCH -next 2/5] " Yang Li
2023-09-01 1:29 ` Yang Li
2023-09-01 1:29 ` [PATCH -next 3/5] drm/amd/display: clean up some inconsistent indentings Yang Li
2023-09-01 1:29 ` Yang Li
2023-09-01 1:29 ` Yang Li [this message]
2023-09-01 1:29 ` [PATCH -next 4/5] " Yang Li
2023-09-01 1:29 ` [PATCH -next 5/5] drm/amd/display: clean up one inconsistent indenting Yang Li
2023-09-01 1:29 ` Yang Li
2023-09-05 17:38 ` Alex Deucher
2023-09-05 17:38 ` Alex Deucher
2023-09-05 17:38 ` Alex Deucher
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