[PATCH 0/7] riscv: ASID-related and UP-related TLB flush enhancements

From: Samuel Holland <samuel@sholland.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	linux-riscv@lists.infradead.org
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	Samuel Holland <samuel@sholland.org>
Subject: [PATCH 0/7] riscv: ASID-related and UP-related TLB flush enhancements
Date: Sat,  9 Sep 2023 15:16:28 -0500	[thread overview]
Message-ID: <20230909201727.10909-1-samuel@sholland.org> (raw)

While reviewing Alexandre Ghiti's "riscv: tlb flush improvements"
series[1], I noticed that the TLB flushing functions mostly end up as
flush_tlb_all() when SMP is disabled. This series resolves that. Along
the way, I realized that we should be using single-ASID flushes wherever
possible, so I implemented that as well. This series is mostly
orthogonal to Alexandre's series, though it does remove the non-ASID
code path from tlbflush.c, which turns out to be required for
flush_tlb_kernel_range().

[1]: https://lore.kernel.org/linux-riscv/20230801085402.1168351-1-alexghiti@rivosinc.com/

Samuel Holland (7):
  riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
  riscv: mm: Introduce cntx2asid/cntx2version helper macros
  riscv: mm: Use a fixed layout for the MM context ID
  riscv: mm: Make asid_bits a local variable
  riscv: mm: Preserve global TLB entries when switching contexts
  riscv: mm: Always flush a single MM context by ASID
  riscv: mm: Combine the SMP and non-SMP TLB flushing code

 arch/riscv/include/asm/errata_list.h | 12 +++-
 arch/riscv/include/asm/mmu.h         |  3 +
 arch/riscv/include/asm/mmu_context.h |  2 -
 arch/riscv/include/asm/tlbflush.h    | 41 ++++++-------
 arch/riscv/mm/Makefile               |  5 +-
 arch/riscv/mm/context.c              | 26 ++++----
 arch/riscv/mm/tlbflush.c             | 92 +++++++---------------------
 7 files changed, 67 insertions(+), 114 deletions(-)

-- 
2.41.0