From: kernel test robot <lkp@intel.com>
To: Samuel Holland <samuel@sholland.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-riscv@lists.infradead.org
Cc: oe-kbuild-all@lists.linux.dev, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
Samuel Holland <samuel@sholland.org>
Subject: Re: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
Date: Sun, 10 Sep 2023 07:02:45 +0800 [thread overview]
Message-ID: <202309100639.tTr4BtGk-lkp@intel.com> (raw)
In-Reply-To: <20230909201727.10909-8-samuel@sholland.org>
Hi Samuel,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.5 next-20230908]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/riscv-Apply-SiFive-CIP-1200-workaround-to-single-ASID-sfence-vma/20230910-042028
base: linus/master
patch link: https://lore.kernel.org/r/20230909201727.10909-8-samuel%40sholland.org
patch subject: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20230910/202309100639.tTr4BtGk-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230910/202309100639.tTr4BtGk-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309100639.tTr4BtGk-lkp@intel.com/
All warnings (new ones prefixed by >>):
arch/riscv/mm/tlbflush.c: In function '__flush_tlb_range':
>> arch/riscv/mm/tlbflush.c:52:22: warning: variable 'cpuid' set but not used [-Wunused-but-set-variable]
52 | unsigned int cpuid;
| ^~~~~
vim +/cpuid +52 arch/riscv/mm/tlbflush.c
18d2199d81054f Anup Patel 2023-03-28 46
18d2199d81054f Anup Patel 2023-03-28 47 static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
c3b2d67046d236 Nanyong Sun 2021-04-30 48 unsigned long size, unsigned long stride)
95594cb40c6e01 Christoph Hellwig 2019-08-21 49 {
ff15058bb4eb32 Samuel Holland 2023-09-09 50 unsigned long asid = cntx2asid(atomic_long_read(&mm->context.id));
70c7605c08c597 Christoph Hellwig 2021-06-06 51 struct cpumask *cmask = mm_cpumask(mm);
31738ede9b339c Atish Patra 2019-08-22 @52 unsigned int cpuid;
95594cb40c6e01 Christoph Hellwig 2019-08-21 53
6384423f49c804 Atish Patra 2019-08-22 54 if (cpumask_empty(cmask))
6384423f49c804 Atish Patra 2019-08-22 55 return;
6384423f49c804 Atish Patra 2019-08-22 56
31738ede9b339c Atish Patra 2019-08-22 57 cpuid = get_cpu();
047bf3010ac2de Samuel Holland 2023-09-09 58 #ifdef CONFIG_SMP
3f1e782998cdf6 Guo Ren 2021-06-06 59 /* check if the tlbflush needs to be sent to other CPUs */
ff15058bb4eb32 Samuel Holland 2023-09-09 60 if (cpumask_any_but(cmask, cpuid) < nr_cpu_ids) {
18d2199d81054f Anup Patel 2023-03-28 61 if (riscv_use_ipi_for_rfence()) {
047bf3010ac2de Samuel Holland 2023-09-09 62 struct flush_tlb_range_data ftd;
047bf3010ac2de Samuel Holland 2023-09-09 63
18d2199d81054f Anup Patel 2023-03-28 64 ftd.asid = asid;
18d2199d81054f Anup Patel 2023-03-28 65 ftd.start = start;
18d2199d81054f Anup Patel 2023-03-28 66 ftd.size = size;
18d2199d81054f Anup Patel 2023-03-28 67 ftd.stride = stride;
18d2199d81054f Anup Patel 2023-03-28 68 on_each_cpu_mask(cmask,
18d2199d81054f Anup Patel 2023-03-28 69 __ipi_flush_tlb_range_asid,
18d2199d81054f Anup Patel 2023-03-28 70 &ftd, 1);
18d2199d81054f Anup Patel 2023-03-28 71 } else
18d2199d81054f Anup Patel 2023-03-28 72 sbi_remote_sfence_vma_asid(cmask,
18d2199d81054f Anup Patel 2023-03-28 73 start, size, asid);
18d2199d81054f Anup Patel 2023-03-28 74 } else
047bf3010ac2de Samuel Holland 2023-09-09 75 #endif
ff15058bb4eb32 Samuel Holland 2023-09-09 76 local_flush_tlb_range_asid(start, size, stride, asid);
31738ede9b339c Atish Patra 2019-08-22 77 put_cpu();
95594cb40c6e01 Christoph Hellwig 2019-08-21 78 }
95594cb40c6e01 Christoph Hellwig 2019-08-21 79
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: Samuel Holland <samuel@sholland.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-riscv@lists.infradead.org
Cc: oe-kbuild-all@lists.linux.dev, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
Samuel Holland <samuel@sholland.org>
Subject: Re: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
Date: Sun, 10 Sep 2023 07:02:45 +0800 [thread overview]
Message-ID: <202309100639.tTr4BtGk-lkp@intel.com> (raw)
In-Reply-To: <20230909201727.10909-8-samuel@sholland.org>
Hi Samuel,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.5 next-20230908]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Samuel-Holland/riscv-Apply-SiFive-CIP-1200-workaround-to-single-ASID-sfence-vma/20230910-042028
base: linus/master
patch link: https://lore.kernel.org/r/20230909201727.10909-8-samuel%40sholland.org
patch subject: [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20230910/202309100639.tTr4BtGk-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230910/202309100639.tTr4BtGk-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309100639.tTr4BtGk-lkp@intel.com/
All warnings (new ones prefixed by >>):
arch/riscv/mm/tlbflush.c: In function '__flush_tlb_range':
>> arch/riscv/mm/tlbflush.c:52:22: warning: variable 'cpuid' set but not used [-Wunused-but-set-variable]
52 | unsigned int cpuid;
| ^~~~~
vim +/cpuid +52 arch/riscv/mm/tlbflush.c
18d2199d81054f Anup Patel 2023-03-28 46
18d2199d81054f Anup Patel 2023-03-28 47 static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
c3b2d67046d236 Nanyong Sun 2021-04-30 48 unsigned long size, unsigned long stride)
95594cb40c6e01 Christoph Hellwig 2019-08-21 49 {
ff15058bb4eb32 Samuel Holland 2023-09-09 50 unsigned long asid = cntx2asid(atomic_long_read(&mm->context.id));
70c7605c08c597 Christoph Hellwig 2021-06-06 51 struct cpumask *cmask = mm_cpumask(mm);
31738ede9b339c Atish Patra 2019-08-22 @52 unsigned int cpuid;
95594cb40c6e01 Christoph Hellwig 2019-08-21 53
6384423f49c804 Atish Patra 2019-08-22 54 if (cpumask_empty(cmask))
6384423f49c804 Atish Patra 2019-08-22 55 return;
6384423f49c804 Atish Patra 2019-08-22 56
31738ede9b339c Atish Patra 2019-08-22 57 cpuid = get_cpu();
047bf3010ac2de Samuel Holland 2023-09-09 58 #ifdef CONFIG_SMP
3f1e782998cdf6 Guo Ren 2021-06-06 59 /* check if the tlbflush needs to be sent to other CPUs */
ff15058bb4eb32 Samuel Holland 2023-09-09 60 if (cpumask_any_but(cmask, cpuid) < nr_cpu_ids) {
18d2199d81054f Anup Patel 2023-03-28 61 if (riscv_use_ipi_for_rfence()) {
047bf3010ac2de Samuel Holland 2023-09-09 62 struct flush_tlb_range_data ftd;
047bf3010ac2de Samuel Holland 2023-09-09 63
18d2199d81054f Anup Patel 2023-03-28 64 ftd.asid = asid;
18d2199d81054f Anup Patel 2023-03-28 65 ftd.start = start;
18d2199d81054f Anup Patel 2023-03-28 66 ftd.size = size;
18d2199d81054f Anup Patel 2023-03-28 67 ftd.stride = stride;
18d2199d81054f Anup Patel 2023-03-28 68 on_each_cpu_mask(cmask,
18d2199d81054f Anup Patel 2023-03-28 69 __ipi_flush_tlb_range_asid,
18d2199d81054f Anup Patel 2023-03-28 70 &ftd, 1);
18d2199d81054f Anup Patel 2023-03-28 71 } else
18d2199d81054f Anup Patel 2023-03-28 72 sbi_remote_sfence_vma_asid(cmask,
18d2199d81054f Anup Patel 2023-03-28 73 start, size, asid);
18d2199d81054f Anup Patel 2023-03-28 74 } else
047bf3010ac2de Samuel Holland 2023-09-09 75 #endif
ff15058bb4eb32 Samuel Holland 2023-09-09 76 local_flush_tlb_range_asid(start, size, stride, asid);
31738ede9b339c Atish Patra 2019-08-22 77 put_cpu();
95594cb40c6e01 Christoph Hellwig 2019-08-21 78 }
95594cb40c6e01 Christoph Hellwig 2019-08-21 79
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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next prev parent reply other threads:[~2023-09-09 23:02 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-09 20:16 [PATCH 0/7] riscv: ASID-related and UP-related TLB flush enhancements Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 1/7] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 2/7] riscv: mm: Introduce cntx2asid/cntx2version helper macros Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 3/7] riscv: mm: Use a fixed layout for the MM context ID Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 4/7] riscv: mm: Make asid_bits a local variable Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 5/7] riscv: mm: Preserve global TLB entries when switching contexts Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 20:16 ` [PATCH 6/7] riscv: mm: Always flush a single MM context by ASID Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-10 19:46 ` Conor Dooley
2023-09-10 19:46 ` Conor Dooley
2023-10-26 15:53 ` Palmer Dabbelt
2023-10-26 15:53 ` Palmer Dabbelt
2023-09-09 20:16 ` [PATCH 7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code Samuel Holland
2023-09-09 20:16 ` Samuel Holland
2023-09-09 23:02 ` kernel test robot [this message]
2023-09-09 23:02 ` kernel test robot
2023-09-11 22:08 ` kernel test robot
2023-09-11 22:08 ` kernel test robot
2023-09-12 2:03 ` kernel test robot
2023-09-12 2:03 ` kernel test robot
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