From: Minda Chen <minda.chen@starfivetech.com> To: "Conor Dooley" <conor@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh+dt@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Daire McNamara" <daire.mcnamara@microchip.com>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-pci@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de>, Mason Huo <mason.huo@starfivetech.com>, Leyfoon Tan <leyfoon.tan@starfivetech.com>, Kevin Xie <kevin.xie@starfivetech.com>, Minda Chen <minda.chen@starfivetech.com> Subject: [PATCH v13 19/21] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Date: Thu, 14 Dec 2023 15:28:37 +0800 [thread overview] Message-ID: <20231214072839.2367-20-minda.chen@starfivetech.com> (raw) In-Reply-To: <20231214072839.2367-1-minda.chen@starfivetech.com> From: Kevin Xie <kevin.xie@starfivetech.com> Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum waiting time between exit from a conventional reset and sending the first configuration request to the device. As described in PCI base specification r6.0, section 6.6.1 <Conventional Reset>, there are two different use cases of the value: - "With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms following exit from a Conventional Reset before sending a Configuration Request to the device immediately below that Port." - "With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port." Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> --- drivers/pci/pci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..06f1f1eb878c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 <Conventional + * Reset>, there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Minda Chen <minda.chen@starfivetech.com> To: "Conor Dooley" <conor@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Rob Herring" <robh+dt@kernel.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Daire McNamara" <daire.mcnamara@microchip.com>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-pci@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de>, Mason Huo <mason.huo@starfivetech.com>, Leyfoon Tan <leyfoon.tan@starfivetech.com>, Kevin Xie <kevin.xie@starfivetech.com>, Minda Chen <minda.chen@starfivetech.com> Subject: [PATCH v13 19/21] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Date: Thu, 14 Dec 2023 15:28:37 +0800 [thread overview] Message-ID: <20231214072839.2367-20-minda.chen@starfivetech.com> (raw) In-Reply-To: <20231214072839.2367-1-minda.chen@starfivetech.com> From: Kevin Xie <kevin.xie@starfivetech.com> Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum waiting time between exit from a conventional reset and sending the first configuration request to the device. As described in PCI base specification r6.0, section 6.6.1 <Conventional Reset>, there are two different use cases of the value: - "With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms following exit from a Conventional Reset before sending a Configuration Request to the device immediately below that Port." - "With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port." Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> Reviewed-by: Mason Huo <mason.huo@starfivetech.com> --- drivers/pci/pci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..06f1f1eb878c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 <Conventional + * Reset>, there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-12-14 7:31 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-12-14 7:28 [PATCH v13 0/21] Refactoring Microchip PCIe driver and add StarFive PCIe Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 01/21] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 02/21] PCI: microchip: Move pcie-microchip-host.c to plda directory Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 03/21] PCI: microchip: Move PLDA IP register macros to pcie-plda.h Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 04/21] PCI: microchip: Add bridge_addr field to struct mc_pcie Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 05/21] PCI: microchip: Rename two PCIe data structures Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 06/21] PCI: microchip: Move PCIe host data structures to plda-pcie.h Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 07/21] PCI: microchip: Rename two setup functions Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 08/21] PCI: microchip: Change the argument of plda_pcie_setup_iomems() Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 09/21] PCI: microchip: Move setup functions to pcie-plda-host.c Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-27 15:49 ` Lorenzo Pieralisi 2023-12-27 15:49 ` Lorenzo Pieralisi 2023-12-28 9:46 ` Minda Chen 2023-12-28 9:46 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 10/21] PCI: microchip: Rename interrupt related functions Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-27 15:52 ` Lorenzo Pieralisi 2023-12-27 15:52 ` Lorenzo Pieralisi 2023-12-29 3:44 ` Minda Chen 2023-12-29 3:44 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 11/21] PCI: microchip: Add num_events field to struct plda_pcie_rp Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-27 15:55 ` Lorenzo Pieralisi 2023-12-27 15:55 ` Lorenzo Pieralisi 2023-12-29 3:46 ` Minda Chen 2023-12-29 3:46 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 12/21] PCI: microchip: Add request_event_irq() callback function Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-27 16:01 ` Lorenzo Pieralisi 2023-12-27 16:01 ` Lorenzo Pieralisi 2023-12-28 11:58 ` Minda Chen 2023-12-28 11:58 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 13/21] PCI: microchip: Add INTx and MSI event num to struct plda_event Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 14/21] PCI: microchip: Add get_events() callback and add PLDA get_event() Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-27 16:31 ` Lorenzo Pieralisi 2023-12-27 16:31 ` Lorenzo Pieralisi 2023-12-28 10:04 ` Minda Chen 2023-12-28 10:04 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 15/21] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-21 10:56 ` Minda Chen 2023-12-21 10:56 ` Minda Chen 2023-12-21 15:32 ` Lorenzo Pieralisi 2023-12-21 15:32 ` Lorenzo Pieralisi 2023-12-22 11:18 ` Minda Chen 2023-12-22 11:18 ` Minda Chen 2023-12-27 12:43 ` Lorenzo Pieralisi 2023-12-27 12:43 ` Lorenzo Pieralisi 2023-12-28 11:25 ` Minda Chen 2023-12-28 11:25 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 16/21] PCI: microchip: Move IRQ functions to pcie-plda-host.c Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 17/21] PCI: plda: Add host init/deinit and map bus functions Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 18/21] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` Minda Chen [this message] 2023-12-14 7:28 ` [PATCH v13 19/21] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Minda Chen 2023-12-27 16:03 ` Lorenzo Pieralisi 2023-12-27 16:03 ` Lorenzo Pieralisi 2023-12-27 19:08 ` Bjorn Helgaas 2023-12-27 19:08 ` Bjorn Helgaas 2023-12-14 7:28 ` [PATCH v13 20/21] PCI: starfive: Add JH7110 PCIe controller Minda Chen 2023-12-14 7:28 ` Minda Chen 2023-12-14 7:28 ` [PATCH v13 21/21] riscv: dts: starfive: add PCIe dts configuration for JH7110 Minda Chen 2023-12-14 7:28 ` Minda Chen 2024-01-03 22:40 ` [PATCH v13 0/21] Refactoring Microchip PCIe driver and add StarFive PCIe Kevin Hilman 2024-01-03 22:40 ` Kevin Hilman 2024-01-05 2:35 ` 回复: " Kevin Xie 2024-01-05 2:35 ` Kevin Xie 2024-01-05 17:28 ` Kevin Hilman 2024-01-05 17:28 ` Kevin Hilman 2024-01-08 10:48 ` 回复: " Kevin Xie 2024-01-08 10:48 ` Kevin Xie 2024-01-10 16:29 ` Emil Renner Berthing 2024-01-10 16:29 ` Emil Renner Berthing
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