All of lore.kernel.org
 help / color / mirror / Atom feed
From: Kevin Hilman <khilman@baylibre.com>
To: "Minda Chen" <minda.chen@starfivetech.com>,
	"Conor Dooley" <conor@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Daire McNamara" <daire.mcnamara@microchip.com>,
	"Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Mason Huo <mason.huo@starfivetech.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Kevin Xie <kevin.xie@starfivetech.com>,
	Minda Chen <minda.chen@starfivetech.com>
Subject: Re: [PATCH v13 0/21] Refactoring Microchip PCIe driver and add StarFive PCIe
Date: Wed, 03 Jan 2024 14:40:36 -0800	[thread overview]
Message-ID: <7hfrzeavmj.fsf@baylibre.com> (raw)
In-Reply-To: <20231214072839.2367-1-minda.chen@starfivetech.com>

Minda Chen <minda.chen@starfivetech.com> writes:

> This patchset final purpose is add PCIe driver for StarFive JH7110 SoC.
> JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the
> same IP and have commit their codes, which are mixed with PLDA
> controller codes and Microchip platform codes.

Thank you for this series.

I tested this on a VisionFive v2 board, and it seems to probe and find my
M.2 NVMe SSD, but then gets timeouts when trying to use the NVMe
(e.g. 'blkid' command)

Kernel logs below.

Kevin

[   15.131094] pcie-starfive 9c0000000.pcie: host bridge /soc/pcie@9c0000000 ranges:
[   15.138637] pcie-starfive 9c0000000.pcie:      MEM 0x0038000000..0x003fffffff -> 0x0038000000
[   15.147180] pcie-starfive 9c0000000.pcie:      MEM 0x0980000000..0x09bfffffff -> 0x0980000000
[   15.368040] pcie-starfive 9c0000000.pcie: port link up
[   15.374219] pcie-starfive 9c0000000.pcie: PCI host bridge to bus 0001:00
[   15.380944] pci_bus 0001:00: root bus resource [bus 00-ff]
[   15.386443] pci_bus 0001:00: root bus resource [mem 0x38000000-0x3fffffff]
[   15.393330] pci_bus 0001:00: root bus resource [mem 0x980000000-0x9bfffffff pref]
[   15.400882] pci 0001:00:00.0: [1556:1111] type 01 class 0x060400
[   15.407165] pci 0001:00:00.0: supports D1 D2
[   15.411447] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[   15.419964] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[   15.428245] pci 0001:01:00.0: [126f:2263] type 00 class 0x010802
[   15.434331] pci 0001:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
[   15.441578] pci 0001:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 31.504 Gb/s with 8
.0 GT/s PCIe x4 link)
[   15.456910] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01
[   15.463553] pci 0001:00:00.0: BAR 8: assigned [mem 0x38000000-0x380fffff]
[   15.470352] pci 0001:01:00.0: BAR 0: assigned [mem 0x38000000-0x38003fff 64bit]
[   15.477699] pci 0001:00:00.0: PCI bridge to [bus 01]
[   15.482686] pci 0001:00:00.0:   bridge window [mem 0x38000000-0x380fffff]
[   15.489632] pcieport 0001:00:00.0: enabling device (0000 -> 0002)
[   15.496038] pcieport 0001:00:00.0: PME: Signaling with IRQ 56
[   15.502472] usb 1-1: new high-speed USB device number 2 using xhci_hcd
[   15.509755] usb usb2-port2: over-current condition
[   15.515883] nvme nvme0: pci function 0001:01:00.0
[   15.520615] nvme 0001:01:00.0: enabling device (0000 -> 0002)
[   15.532685] nvme nvme0: allocated 64 MiB host memory buffer.
[   15.550070] nvme nvme0: 4/0/0 default/read/poll queues
[   15.562992] nvme nvme0: Ignoring bogus Namespace Identifiers
[   15.663327] hub 1-1:1.0: USB hub found
[   15.667320] hub 1-1:1.0: 4 ports detected

[   46.064052] nvme nvme0: I/O 424 QID 3 timeout, completion polled

[   76.784046] nvme nvme0: I/O 425 (I/O Cmd) QID 3 timeout, aborting
[   76.790179] nvme nvme0: I/O 426 (I/O Cmd) QID 3 timeout, aborting
[   76.796294] nvme nvme0: I/O 427 (I/O Cmd) QID 3 timeout, aborting
[   76.802411] nvme nvme0: I/O 428 (I/O Cmd) QID 3 timeout, aborting
[   76.808525] nvme nvme0: I/O 429 (I/O Cmd) QID 3 timeout, aborting


WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: "Minda Chen" <minda.chen@starfivetech.com>,
	"Conor Dooley" <conor@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Daire McNamara" <daire.mcnamara@microchip.com>,
	"Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Mason Huo <mason.huo@starfivetech.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Kevin Xie <kevin.xie@starfivetech.com>,
	Minda Chen <minda.chen@starfivetech.com>
Subject: Re: [PATCH v13 0/21] Refactoring Microchip PCIe driver and add StarFive PCIe
Date: Wed, 03 Jan 2024 14:40:36 -0800	[thread overview]
Message-ID: <7hfrzeavmj.fsf@baylibre.com> (raw)
In-Reply-To: <20231214072839.2367-1-minda.chen@starfivetech.com>

Minda Chen <minda.chen@starfivetech.com> writes:

> This patchset final purpose is add PCIe driver for StarFive JH7110 SoC.
> JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the
> same IP and have commit their codes, which are mixed with PLDA
> controller codes and Microchip platform codes.

Thank you for this series.

I tested this on a VisionFive v2 board, and it seems to probe and find my
M.2 NVMe SSD, but then gets timeouts when trying to use the NVMe
(e.g. 'blkid' command)

Kernel logs below.

Kevin

[   15.131094] pcie-starfive 9c0000000.pcie: host bridge /soc/pcie@9c0000000 ranges:
[   15.138637] pcie-starfive 9c0000000.pcie:      MEM 0x0038000000..0x003fffffff -> 0x0038000000
[   15.147180] pcie-starfive 9c0000000.pcie:      MEM 0x0980000000..0x09bfffffff -> 0x0980000000
[   15.368040] pcie-starfive 9c0000000.pcie: port link up
[   15.374219] pcie-starfive 9c0000000.pcie: PCI host bridge to bus 0001:00
[   15.380944] pci_bus 0001:00: root bus resource [bus 00-ff]
[   15.386443] pci_bus 0001:00: root bus resource [mem 0x38000000-0x3fffffff]
[   15.393330] pci_bus 0001:00: root bus resource [mem 0x980000000-0x9bfffffff pref]
[   15.400882] pci 0001:00:00.0: [1556:1111] type 01 class 0x060400
[   15.407165] pci 0001:00:00.0: supports D1 D2
[   15.411447] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[   15.419964] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[   15.428245] pci 0001:01:00.0: [126f:2263] type 00 class 0x010802
[   15.434331] pci 0001:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
[   15.441578] pci 0001:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 31.504 Gb/s with 8
.0 GT/s PCIe x4 link)
[   15.456910] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01
[   15.463553] pci 0001:00:00.0: BAR 8: assigned [mem 0x38000000-0x380fffff]
[   15.470352] pci 0001:01:00.0: BAR 0: assigned [mem 0x38000000-0x38003fff 64bit]
[   15.477699] pci 0001:00:00.0: PCI bridge to [bus 01]
[   15.482686] pci 0001:00:00.0:   bridge window [mem 0x38000000-0x380fffff]
[   15.489632] pcieport 0001:00:00.0: enabling device (0000 -> 0002)
[   15.496038] pcieport 0001:00:00.0: PME: Signaling with IRQ 56
[   15.502472] usb 1-1: new high-speed USB device number 2 using xhci_hcd
[   15.509755] usb usb2-port2: over-current condition
[   15.515883] nvme nvme0: pci function 0001:01:00.0
[   15.520615] nvme 0001:01:00.0: enabling device (0000 -> 0002)
[   15.532685] nvme nvme0: allocated 64 MiB host memory buffer.
[   15.550070] nvme nvme0: 4/0/0 default/read/poll queues
[   15.562992] nvme nvme0: Ignoring bogus Namespace Identifiers
[   15.663327] hub 1-1:1.0: USB hub found
[   15.667320] hub 1-1:1.0: 4 ports detected

[   46.064052] nvme nvme0: I/O 424 QID 3 timeout, completion polled

[   76.784046] nvme nvme0: I/O 425 (I/O Cmd) QID 3 timeout, aborting
[   76.790179] nvme nvme0: I/O 426 (I/O Cmd) QID 3 timeout, aborting
[   76.796294] nvme nvme0: I/O 427 (I/O Cmd) QID 3 timeout, aborting
[   76.802411] nvme nvme0: I/O 428 (I/O Cmd) QID 3 timeout, aborting
[   76.808525] nvme nvme0: I/O 429 (I/O Cmd) QID 3 timeout, aborting


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2024-01-03 22:40 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-14  7:28 [PATCH v13 0/21] Refactoring Microchip PCIe driver and add StarFive PCIe Minda Chen
2023-12-14  7:28 ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 01/21] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 02/21] PCI: microchip: Move pcie-microchip-host.c to plda directory Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 03/21] PCI: microchip: Move PLDA IP register macros to pcie-plda.h Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 04/21] PCI: microchip: Add bridge_addr field to struct mc_pcie Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 05/21] PCI: microchip: Rename two PCIe data structures Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 06/21] PCI: microchip: Move PCIe host data structures to plda-pcie.h Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 07/21] PCI: microchip: Rename two setup functions Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 08/21] PCI: microchip: Change the argument of plda_pcie_setup_iomems() Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 09/21] PCI: microchip: Move setup functions to pcie-plda-host.c Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-27 15:49   ` Lorenzo Pieralisi
2023-12-27 15:49     ` Lorenzo Pieralisi
2023-12-28  9:46     ` Minda Chen
2023-12-28  9:46       ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 10/21] PCI: microchip: Rename interrupt related functions Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-27 15:52   ` Lorenzo Pieralisi
2023-12-27 15:52     ` Lorenzo Pieralisi
2023-12-29  3:44     ` Minda Chen
2023-12-29  3:44       ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 11/21] PCI: microchip: Add num_events field to struct plda_pcie_rp Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-27 15:55   ` Lorenzo Pieralisi
2023-12-27 15:55     ` Lorenzo Pieralisi
2023-12-29  3:46     ` Minda Chen
2023-12-29  3:46       ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 12/21] PCI: microchip: Add request_event_irq() callback function Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-27 16:01   ` Lorenzo Pieralisi
2023-12-27 16:01     ` Lorenzo Pieralisi
2023-12-28 11:58     ` Minda Chen
2023-12-28 11:58       ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 13/21] PCI: microchip: Add INTx and MSI event num to struct plda_event Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 14/21] PCI: microchip: Add get_events() callback and add PLDA get_event() Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-27 16:31   ` Lorenzo Pieralisi
2023-12-27 16:31     ` Lorenzo Pieralisi
2023-12-28 10:04     ` Minda Chen
2023-12-28 10:04       ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 15/21] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-21 10:56   ` Minda Chen
2023-12-21 10:56     ` Minda Chen
2023-12-21 15:32     ` Lorenzo Pieralisi
2023-12-21 15:32       ` Lorenzo Pieralisi
2023-12-22 11:18       ` Minda Chen
2023-12-22 11:18         ` Minda Chen
2023-12-27 12:43         ` Lorenzo Pieralisi
2023-12-27 12:43           ` Lorenzo Pieralisi
2023-12-28 11:25           ` Minda Chen
2023-12-28 11:25             ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 16/21] PCI: microchip: Move IRQ functions to pcie-plda-host.c Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 17/21] PCI: plda: Add host init/deinit and map bus functions Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 18/21] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 19/21] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-27 16:03   ` Lorenzo Pieralisi
2023-12-27 16:03     ` Lorenzo Pieralisi
2023-12-27 19:08   ` Bjorn Helgaas
2023-12-27 19:08     ` Bjorn Helgaas
2023-12-14  7:28 ` [PATCH v13 20/21] PCI: starfive: Add JH7110 PCIe controller Minda Chen
2023-12-14  7:28   ` Minda Chen
2023-12-14  7:28 ` [PATCH v13 21/21] riscv: dts: starfive: add PCIe dts configuration for JH7110 Minda Chen
2023-12-14  7:28   ` Minda Chen
2024-01-03 22:40 ` Kevin Hilman [this message]
2024-01-03 22:40   ` [PATCH v13 0/21] Refactoring Microchip PCIe driver and add StarFive PCIe Kevin Hilman
2024-01-05  2:35   ` 回复: " Kevin Xie
2024-01-05  2:35     ` Kevin Xie
2024-01-05 17:28     ` Kevin Hilman
2024-01-05 17:28       ` Kevin Hilman
2024-01-08 10:48       ` 回复: " Kevin Xie
2024-01-08 10:48         ` Kevin Xie
2024-01-10 16:29         ` Emil Renner Berthing
2024-01-10 16:29           ` Emil Renner Berthing

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=7hfrzeavmj.fsf@baylibre.com \
    --to=khilman@baylibre.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=bhelgaas@google.com \
    --cc=conor@kernel.org \
    --cc=daire.mcnamara@microchip.com \
    --cc=devicetree@vger.kernel.org \
    --cc=emil.renner.berthing@canonical.com \
    --cc=kevin.xie@starfivetech.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=kw@linux.com \
    --cc=leyfoon.tan@starfivetech.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=lpieralisi@kernel.org \
    --cc=mason.huo@starfivetech.com \
    --cc=minda.chen@starfivetech.com \
    --cc=p.zabel@pengutronix.de \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.