From: "Heiko Stübner" <heiko@sntech.de> To: Douglas Anderson <dianders@chromium.org> Cc: ulf.hansson@linaro.org, kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Date: Mon, 20 Jun 2016 20:14:52 +0200 [thread overview] Message-ID: <2890767.K8G0sjVPM4@diego> (raw) In-Reply-To: <1466445414-11974-15-git-send-email-dianders@chromium.org> Am Montag, 20. Juni 2016, 10:56:53 schrieb Douglas Anderson: > The "phyctrl_frqsel" is described in the Arasan datasheet [1] as "the > frequency range of DLL operation". Although the Rockchip variant of > this PHY has different ranges than the reference Arasan PHY it appears > as if the functionality is similar. We should set this phyctrl field > properly. > > Note: as per Rockchip engineers, apparently the "phyctrl_frqsel" is > actually only useful in HS200 / HS400 modes even though the DLL itself > it used for some purposes in all modes. See the discussion in the > earlier change in this series: ("mmc: sdhci-of-arasan: Always power the > PHY off/on when clock changes"). In any case, it shouldn't hurt to set > this always. > > Note that this change should allow boards to run at HS200 / HS400 speed > modes while running at 100 MHz or 150 MHz. In fact, running HS400 at > 150 MHz (giving 300 MB/s) is the main motivation of this series, since > performance is still good but signal integrity problems are less > prevelant at 150 MHz. > > [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Acked-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > Changes in v3: > - Use phy_init / phy_exit (Heiko) Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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From: heiko@sntech.de (Heiko Stübner) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Date: Mon, 20 Jun 2016 20:14:52 +0200 [thread overview] Message-ID: <2890767.K8G0sjVPM4@diego> (raw) In-Reply-To: <1466445414-11974-15-git-send-email-dianders@chromium.org> Am Montag, 20. Juni 2016, 10:56:53 schrieb Douglas Anderson: > The "phyctrl_frqsel" is described in the Arasan datasheet [1] as "the > frequency range of DLL operation". Although the Rockchip variant of > this PHY has different ranges than the reference Arasan PHY it appears > as if the functionality is similar. We should set this phyctrl field > properly. > > Note: as per Rockchip engineers, apparently the "phyctrl_frqsel" is > actually only useful in HS200 / HS400 modes even though the DLL itself > it used for some purposes in all modes. See the discussion in the > earlier change in this series: ("mmc: sdhci-of-arasan: Always power the > PHY off/on when clock changes"). In any case, it shouldn't hurt to set > this always. > > Note that this change should allow boards to run at HS200 / HS400 speed > modes while running at 100 MHz or 150 MHz. In fact, running HS400 at > 150 MHz (giving 300 MB/s) is the main motivation of this series, since > performance is still good but signal integrity problems are less > prevelant at 150 MHz. > > [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Acked-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > Changes in v3: > - Use phy_init / phy_exit (Heiko) Reviewed-by: Heiko Stuebner <heiko@sntech.de>
next prev parent reply other threads:[~2016-06-20 18:15 UTC|newest] Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-20 17:56 [PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 01/15] phy: rockchip-emmc: give DLL some extra time to be ready Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 19:23 ` Guenter Roeck 2016-06-20 19:23 ` Guenter Roeck 2016-06-20 19:23 ` Guenter Roeck 2016-06-20 19:30 ` Doug Anderson 2016-06-20 19:30 ` Doug Anderson 2016-06-20 19:30 ` Doug Anderson 2016-06-20 19:36 ` Guenter Roeck 2016-06-20 19:36 ` Guenter Roeck 2016-06-20 19:36 ` Guenter Roeck 2016-06-20 19:38 ` Doug Anderson 2016-06-20 19:38 ` Doug Anderson 2016-06-20 19:38 ` Doug Anderson 2016-06-20 17:56 ` [PATCH v3 02/15] phy: rockchip-emmc: configure frequency range and drive impedance Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 03/15] phy: rockchip-emmc: configure default output tap delay Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 05/15] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 19:29 ` Guenter Roeck 2016-06-20 19:29 ` Guenter Roeck 2016-06-20 19:29 ` Guenter Roeck 2016-06-20 19:36 ` Doug Anderson 2016-06-20 19:36 ` Doug Anderson 2016-06-20 19:36 ` Doug Anderson 2016-06-20 19:38 ` Guenter Roeck 2016-06-20 19:38 ` Guenter Roeck 2016-06-20 19:38 ` Guenter Roeck 2016-06-20 17:56 ` [PATCH v3 06/15] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-22 12:34 ` Adrian Hunter 2016-06-22 12:34 ` Adrian Hunter 2016-06-22 12:34 ` Adrian Hunter 2016-06-20 17:56 ` [PATCH v3 07/15] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 08/15] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-22 12:34 ` Adrian Hunter 2016-06-22 12:34 ` Adrian Hunter 2016-06-20 17:56 ` [PATCH v3 09/15] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-22 16:30 ` Heiko Stübner 2016-06-22 16:30 ` Heiko Stübner 2016-06-20 17:56 ` [PATCH v3 10/15] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 11/15] " Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-22 12:35 ` Adrian Hunter 2016-06-22 12:35 ` Adrian Hunter 2016-06-20 17:56 ` [PATCH v3 12/15] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 13/15] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off() Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` [PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 18:14 ` Heiko Stübner [this message] 2016-06-20 18:14 ` Heiko Stübner 2016-06-20 17:56 ` [PATCH v3 15/15] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-20 17:56 ` Douglas Anderson 2016-06-22 16:31 ` Heiko Stübner 2016-06-22 16:31 ` Heiko Stübner 2016-06-22 16:31 ` Heiko Stübner 2016-06-20 18:17 ` [PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399 Heiko Stübner 2016-06-20 18:17 ` Heiko Stübner 2016-06-22 15:23 ` Ulf Hansson 2016-06-22 15:23 ` Ulf Hansson 2016-06-22 15:23 ` Ulf Hansson
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