From: Conor Dooley <conor@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>
Cc: Xingyu Wu <xingyu.wu@starfivetech.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110
Date: Wed, 15 Mar 2023 22:48:55 +0000 [thread overview]
Message-ID: <2df1dc9c-b063-42a2-b74f-590c9421f4f2@spud> (raw)
In-Reply-To: <e24f9d404c5f9830c9606e4635dc6431.sboyd@kernel.org>
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On Wed, Mar 15, 2023 at 03:40:00PM -0700, Stephen Boyd wrote:
> Quoting Conor Dooley (2023-03-15 01:14:06)
> > At what point does that become too much to go via soc and some sort of
> > shared tag become needed?
> BTW, clk driver code doesn't typically go via soc. Not sure if that's
> happening but please don't do that.
Perfect, shan't.
> Platform/SoC maintainers either base their DTS file branch on some
> branch made in clk repo that has the bindings and drivers they need
> (clk-starfive probably), or they send a pull request to clk maintainers
> with the bindings and clk drivers. Or they don't use the #defines in the
> header files and use raw numbers in the DTS, or they simply apply the
> patch that just has the #defines in it to their SoC tree and we
> duplicate the commit in the history by also applying it to the clk tree.
>
> Let's try to keep things simple and not use raw numbers.
Definitely not!
I'll do something sane with Emil once the base series is ready.
Just was not sure how you typically liked this stuff to go, and now I am
sure of what you do not want!
Thanks,
Conor.
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>
Cc: Xingyu Wu <xingyu.wu@starfivetech.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110
Date: Wed, 15 Mar 2023 22:48:55 +0000 [thread overview]
Message-ID: <2df1dc9c-b063-42a2-b74f-590c9421f4f2@spud> (raw)
In-Reply-To: <e24f9d404c5f9830c9606e4635dc6431.sboyd@kernel.org>
[-- Attachment #1.1: Type: text/plain, Size: 1138 bytes --]
On Wed, Mar 15, 2023 at 03:40:00PM -0700, Stephen Boyd wrote:
> Quoting Conor Dooley (2023-03-15 01:14:06)
> > At what point does that become too much to go via soc and some sort of
> > shared tag become needed?
> BTW, clk driver code doesn't typically go via soc. Not sure if that's
> happening but please don't do that.
Perfect, shan't.
> Platform/SoC maintainers either base their DTS file branch on some
> branch made in clk repo that has the bindings and drivers they need
> (clk-starfive probably), or they send a pull request to clk maintainers
> with the bindings and clk drivers. Or they don't use the #defines in the
> header files and use raw numbers in the DTS, or they simply apply the
> patch that just has the #defines in it to their SoC tree and we
> duplicate the commit in the history by also applying it to the clk tree.
>
> Let's try to keep things simple and not use raw numbers.
Definitely not!
I'll do something sane with Emil once the base series is ready.
Just was not sure how you typically liked this stuff to go, and now I am
sure of what you do not want!
Thanks,
Conor.
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next prev parent reply other threads:[~2023-03-15 22:49 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-14 12:43 [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-15 7:55 ` Krzysztof Kozlowski
2023-03-15 7:55 ` Krzysztof Kozlowski
2023-03-14 12:43 ` [PATCH v3 02/11] reset: starfive: jh7110: Add StarFive System-Top-Group reset support Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 03/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 04/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 05/11] reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-14 12:43 ` [PATCH v3 06/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
2023-03-14 12:43 ` Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 07/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
2023-03-14 12:44 ` Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 08/11] reset: starfive: jh7110: Add StarFive Video-Output reset support Xingyu Wu
2023-03-14 12:44 ` Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
2023-03-14 12:44 ` Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-03-14 12:44 ` Xingyu Wu
2023-03-14 12:44 ` [PATCH v3 11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
2023-03-14 12:44 ` Xingyu Wu
2023-03-15 0:30 ` [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110 Stephen Boyd
2023-03-15 0:30 ` Stephen Boyd
2023-03-15 3:44 ` Xingyu Wu
2023-03-15 3:44 ` Xingyu Wu
2023-03-15 8:14 ` Conor Dooley
2023-03-15 8:14 ` Conor Dooley
2023-03-15 22:40 ` Stephen Boyd
2023-03-15 22:40 ` Stephen Boyd
2023-03-15 22:48 ` Conor Dooley [this message]
2023-03-15 22:48 ` Conor Dooley
2023-03-15 22:48 ` Stephen Boyd
2023-03-15 22:48 ` Stephen Boyd
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