All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Cédric Le Goater" <clg@kaod.org>
To: Saif Abrar <saif.abrar@linux.vnet.ibm.com>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com,
	marcel.apfelbaum@gmail.com, cohuck@redhat.com,
	pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com
Subject: Re: [PATCH 01/10] qtest/phb4: Add testbench for PHB4
Date: Mon, 25 Mar 2024 10:39:21 +0100	[thread overview]
Message-ID: <3fc15c01-82d4-4243-b6fd-95cb9d2f5548@kaod.org> (raw)
In-Reply-To: <20240321100422.5347-2-saif.abrar@linux.vnet.ibm.com>

Hello Saif,

On 3/21/24 11:04, Saif Abrar wrote:
> New qtest TB added for PHB4.
> TB reads PHB Version register and asserts that
> bits[24:31] have value 0xA5.
> 
> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
> ---
>   tests/qtest/meson.build     |  1 +
>   tests/qtest/pnv-phb4-test.c | 74 +++++++++++++++++++++++++++++++++++++
>   2 files changed, 75 insertions(+)
>   create mode 100644 tests/qtest/pnv-phb4-test.c
> 
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 36c5c13a7b..4795e51c17 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -168,6 +168,7 @@ qtests_ppc64 = \
>     (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) +               \
>     (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) +                 \
>     (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : []) +              \
> +  (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) +                  \
>     (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) +                      \
>     (slirp.found() ? ['pxe-test'] : []) +              \
>     (config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : []) +             \
> diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c
> new file mode 100644
> index 0000000000..e3b809e9c4
> --- /dev/null
> +++ b/tests/qtest/pnv-phb4-test.c
> @@ -0,0 +1,74 @@
> +/*
> + * QTest testcase for PowerNV PHB4
> + *
> + * Copyright (c) 2024, IBM Corporation.
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "libqtest.h"
> +#include "hw/pci-host/pnv_phb4_regs.h"
> +
> +#define P10_XSCOM_BASE          0x000603fc00000000ull
> +#define PHB4_MMIO               0x000600c3c0000000ull
> +#define PHB4_XSCOM              0x8010900ull
> +
> +#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
> +#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> +
> +static uint64_t pnv_xscom_addr(uint32_t pcba)
> +{
> +    return P10_XSCOM_BASE | ((uint64_t) pcba << 3);
> +}
> +
> +static uint64_t pnv_phb4_xscom_addr(uint32_t reg)
> +{
> +    return pnv_xscom_addr(PHB4_XSCOM + reg);
> +}

Please use tests/qtest/pnv-xscom.h instead.

> +/*
> + * XSCOM read/write is indirect in PHB4:
> + * Write 'SCOM - HV Indirect Address Register'
> + * with register-offset to read/write.
> +   - bit[0]: Valid Bit
> +   - bit[51:61]: Indirect Address(00:10)
> + * Read/write 'SCOM - HV Indirect Data Register' to get/set the value.
> + */
> +
> +static uint64_t pnv_phb4_xscom_read(QTestState *qts, uint32_t reg)
> +{
> +    qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR),
> +            PPC_BIT(0) | reg);
> +    return qtest_readq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_DATA));
> +}

> +/* Assert that 'PHB - Version Register Offset 0x0800' bits-[24:31] are 0xA5 */
> +static void phb4_version_test(QTestState *qts)
> +{
> +    uint64_t ver = pnv_phb4_xscom_read(qts, PHB_VERSION);
> +
> +    /* PHB Version register [24:31]: Major Revision ID 0xA5 */
> +    ver = ver >> (63 - 31);
> +    g_assert_cmpuint(ver, ==, 0xA5);
> +}
> +
> +static void test_phb4(void)
> +{
> +    QTestState *qts = NULL;
> +
> +    qts = qtest_initf("-machine powernv10 -accel tcg -nographic -d unimp");

"-nographic -d unimp" is not needed.

> +
> +    /* Make sure test is running on PHB */
> +    phb4_version_test(qts);

Please add similar tests for phb[345]. See tests/qtest/pnv-xscom-test.c.

Thanks,

C.


> +
> +    qtest_quit(qts);
> +}
> +
> +int main(int argc, char **argv)
> +{
> +    g_test_init(&argc, &argv, NULL);
> +    qtest_add_func("phb4", test_phb4);
> +    return g_test_run();
> +}



  reply	other threads:[~2024-03-25  9:40 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-21 10:04 [PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5 Saif Abrar
2024-03-21 10:04 ` [PATCH 01/10] qtest/phb4: Add testbench for PHB4 Saif Abrar
2024-03-25  9:39   ` Cédric Le Goater [this message]
2024-03-21 10:04 ` [PATCH 02/10] pnv/phb4: Add reset logic to PHB4 Saif Abrar
2024-03-25 13:32   ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 03/10] pnv/phb4: Implement sticky reset logic in PHB4 Saif Abrar
2024-03-21 10:04 ` [PATCH 04/10] pnv/phb4: Implement read-only and write-only bits of registers Saif Abrar
2024-03-25 14:15   ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 05/10] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read Saif Abrar
2024-03-25 13:58   ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 06/10] pnv/phb4: Set link-active status in HPSTAT and LMR registers Saif Abrar
2024-03-21 10:04 ` [PATCH 07/10] pnv/phb4: Set link speed and width in the DLP training control register Saif Abrar
2024-03-25 13:36   ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 08/10] pnv/phb4: Implement IODA PCT table Saif Abrar
2024-03-25 13:35   ` Cédric Le Goater
2024-03-21 10:04 ` [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register Saif Abrar
2024-03-25 13:35   ` Cédric Le Goater
2024-03-25 14:37     ` Cornelia Huck
2024-03-21 10:04 ` [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Saif Abrar
2024-03-25 13:34   ` Cédric Le Goater
2024-03-27  9:59     ` Saif Abrar
2024-03-27 16:19       ` Cédric Le Goater
2024-03-28  9:31     ` Saif Abrar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=3fc15c01-82d4-4243-b6fd-95cb9d2f5548@kaod.org \
    --to=clg@kaod.org \
    --cc=cohuck@redhat.com \
    --cc=fbarrat@linux.ibm.com \
    --cc=lvivier@redhat.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=mst@redhat.com \
    --cc=npiggin@gmail.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=saif.abrar@linux.vnet.ibm.com \
    --cc=thuth@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.