From: <Conor.Dooley@microchip.com> To: <jszhang@kernel.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <anup@brainfault.org>, <atishp@atishpatra.org>, <bigeasy@linutronix.de>, <tglx@linutronix.de>, <rostedt@goodmis.org> Cc: <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org> Subject: Re: [PATCH v2 0/5] riscv: add PREEMPT_RT support Date: Thu, 1 Sep 2022 16:41:52 +0000 [thread overview] Message-ID: <4488b1ec-aa34-4be5-3b9b-c65f052f5270@microchip.com> (raw) In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> On 31/08/2022 18:59, Jisheng Zhang wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > This series is to add PREEMPT_RT support to riscv: > patch1 adds the missing number of signal exits in vCPU stat > patch2 switches to the generic guest entry infrastructure > patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for > RT > patch4 adds lazy preempt support > patch5 allows to enable PREEMPT_RT > What version of the preempt_rt patch did you test this with? Maybe I am missing something, but I gave this a whirl with v6.0-rc3 + v6.0-rc3-rt5 & was meant by a bunch of complaints. I am not familiar with the preempt_rt patch, so I am not sure what level of BUG()s or WARNING()s are to be expected, but I saw a fair few... Thanks, Conor. > I assume patch1, patch2 and patch3 can be reviewed and merged for > riscv-next, patch4 and patch5 can be reviewed and maintained in rt tree, > and finally merged once the remaining patches in rt tree are all > mainlined. > > Since v1: > - send to related maillist, I press ENTER too quickly when sending v1 > - remove the signal_pending() handling because that's covered by > generic guest entry infrastructure > > Jisheng Zhang (5): > RISC-V: KVM: Record number of signal exits as a vCPU stat > RISC-V: KVM: Use generic guest entry infrastructure > riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK > riscv: add lazy preempt support > riscv: Allow to enable RT > > arch/riscv/Kconfig | 3 +++ > arch/riscv/include/asm/kvm_host.h | 1 + > arch/riscv/include/asm/thread_info.h | 7 +++++-- > arch/riscv/kernel/asm-offsets.c | 1 + > arch/riscv/kernel/entry.S | 9 +++++++-- > arch/riscv/kvm/Kconfig | 1 + > arch/riscv/kvm/vcpu.c | 18 +++++++----------- > 7 files changed, 25 insertions(+), 15 deletions(-) > > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com> To: <jszhang@kernel.org>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <anup@brainfault.org>, <atishp@atishpatra.org>, <bigeasy@linutronix.de>, <tglx@linutronix.de>, <rostedt@goodmis.org> Cc: <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org> Subject: Re: [PATCH v2 0/5] riscv: add PREEMPT_RT support Date: Thu, 1 Sep 2022 16:41:52 +0000 [thread overview] Message-ID: <4488b1ec-aa34-4be5-3b9b-c65f052f5270@microchip.com> (raw) In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> On 31/08/2022 18:59, Jisheng Zhang wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > This series is to add PREEMPT_RT support to riscv: > patch1 adds the missing number of signal exits in vCPU stat > patch2 switches to the generic guest entry infrastructure > patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for > RT > patch4 adds lazy preempt support > patch5 allows to enable PREEMPT_RT > What version of the preempt_rt patch did you test this with? Maybe I am missing something, but I gave this a whirl with v6.0-rc3 + v6.0-rc3-rt5 & was meant by a bunch of complaints. I am not familiar with the preempt_rt patch, so I am not sure what level of BUG()s or WARNING()s are to be expected, but I saw a fair few... Thanks, Conor. > I assume patch1, patch2 and patch3 can be reviewed and merged for > riscv-next, patch4 and patch5 can be reviewed and maintained in rt tree, > and finally merged once the remaining patches in rt tree are all > mainlined. > > Since v1: > - send to related maillist, I press ENTER too quickly when sending v1 > - remove the signal_pending() handling because that's covered by > generic guest entry infrastructure > > Jisheng Zhang (5): > RISC-V: KVM: Record number of signal exits as a vCPU stat > RISC-V: KVM: Use generic guest entry infrastructure > riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK > riscv: add lazy preempt support > riscv: Allow to enable RT > > arch/riscv/Kconfig | 3 +++ > arch/riscv/include/asm/kvm_host.h | 1 + > arch/riscv/include/asm/thread_info.h | 7 +++++-- > arch/riscv/kernel/asm-offsets.c | 1 + > arch/riscv/kernel/entry.S | 9 +++++++-- > arch/riscv/kvm/Kconfig | 1 + > arch/riscv/kvm/vcpu.c | 18 +++++++----------- > 7 files changed, 25 insertions(+), 15 deletions(-) > > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-01 16:42 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-31 17:59 [PATCH v2 0/5] riscv: add PREEMPT_RT support Jisheng Zhang 2022-08-31 17:59 ` Jisheng Zhang 2022-08-31 17:59 ` [PATCH v2 1/5] RISC-V: KVM: Record number of signal exits as a vCPU stat Jisheng Zhang 2022-08-31 17:59 ` Jisheng Zhang 2022-08-31 17:59 ` [PATCH v2 2/5] RISC-V: KVM: Use generic guest entry infrastructure Jisheng Zhang 2022-08-31 17:59 ` Jisheng Zhang 2022-08-31 17:59 ` [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Jisheng Zhang 2022-08-31 17:59 ` Jisheng Zhang 2022-08-31 17:59 ` [PATCH v2 4/5] riscv: add lazy preempt support Jisheng Zhang 2022-08-31 17:59 ` Jisheng Zhang 2022-09-04 15:16 ` Guo Ren 2022-09-04 15:16 ` Guo Ren 2022-09-05 6:34 ` Sebastian Andrzej Siewior 2022-09-05 6:34 ` Sebastian Andrzej Siewior 2022-09-05 8:33 ` Guo Ren 2022-09-05 8:33 ` Guo Ren 2022-09-05 8:46 ` Sebastian Andrzej Siewior 2022-09-05 8:46 ` Sebastian Andrzej Siewior 2022-09-06 1:46 ` Guo Ren 2022-09-06 1:46 ` Guo Ren 2022-09-05 12:58 ` Jisheng Zhang 2022-09-05 12:58 ` Jisheng Zhang 2022-08-31 17:59 ` [PATCH v2 5/5] riscv: Allow to enable RT Jisheng Zhang 2022-08-31 17:59 ` Jisheng Zhang 2022-09-01 7:04 ` [PATCH v2 0/5] riscv: add PREEMPT_RT support Sebastian Andrzej Siewior 2022-09-01 7:04 ` Sebastian Andrzej Siewior 2022-09-01 13:44 ` Jisheng Zhang 2022-09-01 13:44 ` Jisheng Zhang 2022-09-01 16:41 ` Conor.Dooley [this message] 2022-09-01 16:41 ` Conor.Dooley 2022-09-02 13:09 ` Jisheng Zhang 2022-09-02 13:09 ` Jisheng Zhang 2022-09-02 13:29 ` Conor.Dooley 2022-09-02 13:29 ` Conor.Dooley 2022-11-11 14:32 ` Sebastian Andrzej Siewior 2022-11-11 14:32 ` Sebastian Andrzej Siewior 2022-11-11 14:34 ` Conor.Dooley 2022-11-11 14:34 ` Conor.Dooley 2022-11-12 21:40 ` Conor.Dooley 2022-11-12 21:40 ` Conor.Dooley 2023-03-14 13:07 ` Schaffner, Tobias 2023-03-14 13:07 ` Schaffner, Tobias
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