From: Pu Wen <puwen@hygon.cn> To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com, bp@alien8.de, pbonzini@redhat.com, mchehab@kernel.org, mikhail.jin@gmail.com Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-edac@vger.kernel.org, Pu Wen <puwen@hygon.cn> Subject: [PATCH v5 15/16] driver/edac: enable Hygon support to AMD64 EDAC driver Date: Wed, 29 Aug 2018 20:45:45 +0800 [thread overview] Message-ID: <47e08d8bab1cef667be3955941e7eedc23187ae1.1535459013.git.puwen@hygon.cn> (raw) In-Reply-To: <cover.1535459012.git.puwen@hygon.cn> To make AMD64 EDAC and MCE drivers working on Hygon platforms, add support for Hygon by using the code path of AMD family 0x17. As Hygon will negotiate with AMD to make sure that only Hygon will use family 0x18, under this consideration try to minimize code modifications and share most codes with AMD. Also Hygon PCI Device ID DF_F0/DF_F6(0x1460/0x1466) of Host bridges is needed for edac driver. Signed-off-by: Pu Wen <puwen@hygon.cn> --- drivers/edac/amd64_edac.c | 20 +++++++++++++++++++- drivers/edac/amd64_edac.h | 4 ++++ drivers/edac/mce_amd.c | 4 +++- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 18aeabb..d8b4b0e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) scrubval = scrubrates[i].scrubval; - if (pvt->fam == 0x17) { + if (pvt->fam == 0x17 || pvt->fam == 0x18) { __f17h_set_scrubval(pvt, scrubval); } else if (pvt->fam == 0x15 && pvt->model == 0x60) { f15h_select_dct(pvt, 0); @@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci) break; case 0x17: + case 0x18: amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); if (scrubval & BIT(0)) { amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); @@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt) goto ddr3; case 0x17: + case 0x18: if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) pvt->dram_type = MEM_LRDDR4; else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) @@ -2200,6 +2202,16 @@ static struct amd64_family_type family_types[] = { .dbam_to_cs = f17_base_addr_to_cs_size, } }, + [HYGON_F18_CPUS] = { + /* Hygon F18h uses the same AMD F17h support */ + .ctl_name = "Hygon_F18h", + .f0_id = PCI_DEVICE_ID_HYGON_18H_DF_F0, + .f6_id = PCI_DEVICE_ID_HYGON_18H_DF_F6, + .ops = { + .early_channel_count = f17_early_channel_count, + .dbam_to_cs = f17_base_addr_to_cs_size, + } + }, }; /* @@ -3192,6 +3204,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) pvt->ops = &family_types[F17_CPUS].ops; break; + case 0x18: + fam_type = &family_types[HYGON_F18_CPUS]; + pvt->ops = &family_types[HYGON_F18_CPUS].ops; + break; + default: amd64_err("Unsupported family!\n"); return NULL; @@ -3428,6 +3445,7 @@ static const struct x86_cpu_id amd64_cpuids[] = { { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, + { X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { } }; MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 1d4b74e..6e5f609 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -116,6 +116,9 @@ #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 +#define PCI_DEVICE_ID_HYGON_18H_DF_F0 0x1460 +#define PCI_DEVICE_ID_HYGON_18H_DF_F6 0x1466 + /* * Function 1 - Address Map */ @@ -281,6 +284,7 @@ enum amd_families { F16_CPUS, F16_M30H_CPUS, F17_CPUS, + HYGON_F18_CPUS, NUM_FAMILIES, }; diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 2ab4d61..c605089 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1059,7 +1059,8 @@ static int __init mce_amd_init(void) { struct cpuinfo_x86 *c = &boot_cpu_data; - if (c->x86_vendor != X86_VENDOR_AMD) + if (c->x86_vendor != X86_VENDOR_AMD && + c->x86_vendor != X86_VENDOR_HYGON) return -ENODEV; fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); @@ -1113,6 +1114,7 @@ static int __init mce_amd_init(void) break; case 0x17: + case 0x18: xec_mask = 0x3f; if (!boot_cpu_has(X86_FEATURE_SMCA)) { printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n"); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Pu Wen <puwen@hygon.cn> To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com, bp@alien8.de, pbonzini@redhat.com, mchehab@kernel.org, mikhail.jin@gmail.com Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-edac@vger.kernel.org, Pu Wen <puwen@hygon.cn> Subject: [v5,15/16] driver/edac: enable Hygon support to AMD64 EDAC driver Date: Wed, 29 Aug 2018 20:45:45 +0800 [thread overview] Message-ID: <47e08d8bab1cef667be3955941e7eedc23187ae1.1535459013.git.puwen@hygon.cn> (raw) To make AMD64 EDAC and MCE drivers working on Hygon platforms, add support for Hygon by using the code path of AMD family 0x17. As Hygon will negotiate with AMD to make sure that only Hygon will use family 0x18, under this consideration try to minimize code modifications and share most codes with AMD. Also Hygon PCI Device ID DF_F0/DF_F6(0x1460/0x1466) of Host bridges is needed for edac driver. Signed-off-by: Pu Wen <puwen@hygon.cn> --- drivers/edac/amd64_edac.c | 20 +++++++++++++++++++- drivers/edac/amd64_edac.h | 4 ++++ drivers/edac/mce_amd.c | 4 +++- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 18aeabb..d8b4b0e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) scrubval = scrubrates[i].scrubval; - if (pvt->fam == 0x17) { + if (pvt->fam == 0x17 || pvt->fam == 0x18) { __f17h_set_scrubval(pvt, scrubval); } else if (pvt->fam == 0x15 && pvt->model == 0x60) { f15h_select_dct(pvt, 0); @@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci) break; case 0x17: + case 0x18: amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); if (scrubval & BIT(0)) { amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); @@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt) goto ddr3; case 0x17: + case 0x18: if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) pvt->dram_type = MEM_LRDDR4; else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) @@ -2200,6 +2202,16 @@ static struct amd64_family_type family_types[] = { .dbam_to_cs = f17_base_addr_to_cs_size, } }, + [HYGON_F18_CPUS] = { + /* Hygon F18h uses the same AMD F17h support */ + .ctl_name = "Hygon_F18h", + .f0_id = PCI_DEVICE_ID_HYGON_18H_DF_F0, + .f6_id = PCI_DEVICE_ID_HYGON_18H_DF_F6, + .ops = { + .early_channel_count = f17_early_channel_count, + .dbam_to_cs = f17_base_addr_to_cs_size, + } + }, }; /* @@ -3192,6 +3204,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) pvt->ops = &family_types[F17_CPUS].ops; break; + case 0x18: + fam_type = &family_types[HYGON_F18_CPUS]; + pvt->ops = &family_types[HYGON_F18_CPUS].ops; + break; + default: amd64_err("Unsupported family!\n"); return NULL; @@ -3428,6 +3445,7 @@ static const struct x86_cpu_id amd64_cpuids[] = { { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, + { X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { } }; MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 1d4b74e..6e5f609 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -116,6 +116,9 @@ #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 +#define PCI_DEVICE_ID_HYGON_18H_DF_F0 0x1460 +#define PCI_DEVICE_ID_HYGON_18H_DF_F6 0x1466 + /* * Function 1 - Address Map */ @@ -281,6 +284,7 @@ enum amd_families { F16_CPUS, F16_M30H_CPUS, F17_CPUS, + HYGON_F18_CPUS, NUM_FAMILIES, }; diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 2ab4d61..c605089 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1059,7 +1059,8 @@ static int __init mce_amd_init(void) { struct cpuinfo_x86 *c = &boot_cpu_data; - if (c->x86_vendor != X86_VENDOR_AMD) + if (c->x86_vendor != X86_VENDOR_AMD && + c->x86_vendor != X86_VENDOR_HYGON) return -ENODEV; fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); @@ -1113,6 +1114,7 @@ static int __init mce_amd_init(void) break; case 0x17: + case 0x18: xec_mask = 0x3f; if (!boot_cpu_has(X86_FEATURE_SMCA)) { printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
next prev parent reply other threads:[~2018-08-29 12:46 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-29 12:42 [PATCH v5 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen 2018-08-29 12:42 ` [PATCH v5 01/16] x86/cpu: create Dhyana init file and register new cpu_dev to system Pu Wen 2018-08-29 19:35 ` Andi Kleen 2018-08-30 17:40 ` Pu Wen 2018-08-30 12:35 ` Borislav Petkov 2018-08-30 18:02 ` Pu Wen 2018-08-29 12:43 ` [PATCH v5 02/16] x86/cache: get cache size/leaves and setup cache cpumap for Dhyana Pu Wen 2018-09-03 9:57 ` Borislav Petkov 2018-09-03 12:59 ` Pu Wen 2018-08-29 12:43 ` [PATCH v5 03/16] x86/mtrr: get MTRR number and support TOP_MEM2 Pu Wen 2018-09-03 19:04 ` Borislav Petkov 2018-09-04 3:02 ` Pu Wen 2018-09-04 8:02 ` Borislav Petkov 2018-09-04 12:43 ` Pu Wen 2018-08-29 12:43 ` [PATCH v5 04/16] x86/smpboot: smp init nodelay and no flush caches before sleep Pu Wen 2018-09-04 9:15 ` Borislav Petkov 2018-08-29 12:43 ` [PATCH v5 05/16] x86/pmu: enable Hygon support to PMU infrastructure Pu Wen 2018-09-04 10:48 ` Borislav Petkov 2018-09-04 13:32 ` Pu Wen 2018-08-29 12:44 ` [PATCH v5 06/16] x86/nops: init ideal_nops for Hygon Pu Wen 2018-09-04 14:01 ` Borislav Petkov 2018-08-29 12:44 ` [PATCH v5 07/16] x86/pci: add Hygon PCI vendor and northbridge support Pu Wen 2018-09-04 14:52 ` Borislav Petkov 2018-09-04 15:45 ` Pu Wen 2018-09-04 16:03 ` Borislav Petkov 2018-08-29 12:44 ` [PATCH v5 08/16] x86/apic: add modern APIC support for Hygon Pu Wen 2018-09-04 18:33 ` Borislav Petkov 2018-09-05 8:08 ` Pu Wen 2018-08-29 12:44 ` [PATCH v5 09/16] x86/bugs: add lfence mitigation to spectre v2 and no meltdown " Pu Wen 2018-09-05 9:13 ` Borislav Petkov 2018-09-05 10:40 ` Pu Wen 2018-08-29 12:44 ` [PATCH v5 10/16] x86/mce: enable Hygon support to MCE infrastructure Pu Wen 2018-08-29 12:44 ` [v5,10/16] " Pu Wen 2018-09-05 9:22 ` [PATCH v5 10/16] " Borislav Petkov 2018-09-05 9:22 ` [v5,10/16] " Borislav Petkov 2018-09-05 12:59 ` [PATCH v5 10/16] " Pu Wen 2018-09-05 12:59 ` [v5,10/16] " Pu Wen 2018-09-05 13:15 ` [PATCH v5 10/16] " Borislav Petkov 2018-09-05 13:15 ` [v5,10/16] " Borislav Petkov 2018-09-06 3:52 ` [PATCH v5 10/16] " Pu Wen 2018-09-06 3:52 ` [v5,10/16] " Pu Wen 2018-09-06 8:39 ` [PATCH v5 10/16] " Borislav Petkov 2018-09-06 8:39 ` [v5,10/16] " Borislav Petkov 2018-09-06 11:40 ` [PATCH v5 10/16] " Pu Wen 2018-09-06 11:40 ` [v5,10/16] " Pu Wen 2018-09-06 12:29 ` [PATCH v5 10/16] " Borislav Petkov 2018-09-06 12:29 ` [v5,10/16] " Borislav Petkov 2018-09-06 15:47 ` [PATCH v5 10/16] " Pu Wen 2018-09-06 15:47 ` [v5,10/16] " Pu Wen 2018-08-29 12:45 ` [PATCH v5 11/16] x86/kvm: enable Hygon support to KVM infrastructure Pu Wen 2018-09-05 10:30 ` Borislav Petkov 2018-08-29 12:45 ` [PATCH v5 12/16] x86/xen: enable Hygon support to Xen Pu Wen 2018-08-29 12:45 ` Pu Wen 2018-08-29 12:45 ` [PATCH v5 13/16] driver/acpi: enable Hygon support to ACPI driver Pu Wen 2018-08-29 12:45 ` [PATCH v5 14/16] driver/cpufreq: enable Hygon support to cpufreq driver Pu Wen 2018-08-29 12:45 ` Pu Wen [this message] 2018-08-29 12:45 ` [v5,15/16] driver/edac: enable Hygon support to AMD64 EDAC driver Pu Wen 2018-09-05 10:44 ` [PATCH v5 15/16] " Borislav Petkov 2018-09-05 10:44 ` [v5,15/16] " Borislav Petkov 2018-09-05 13:03 ` [PATCH v5 15/16] " Pu Wen 2018-09-05 13:03 ` [v5,15/16] " Pu Wen 2018-08-29 12:45 ` [PATCH v5 16/16] tools/cpupower: enable Hygon support to cpupower tool Pu Wen
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