From: Eric Auger <eric.auger@linaro.org> To: Andre Przywara <andre.przywara@arm.com>, marc.zyngier@arm.com, christoffer.dall@linaro.org, kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 07/15] KVM: arm64: handle ITS related GICv3 redistributor registers Date: Thu, 13 Aug 2015 14:17:38 +0200 [thread overview] Message-ID: <55CC8AE2.2070807@linaro.org> (raw) In-Reply-To: <1436538111-4294-8-git-send-email-andre.przywara@arm.com> On 07/10/2015 04:21 PM, Andre Przywara wrote: > In the GICv3 redistributor there are the PENDBASER and PROPBASER > registers which we did not emulate so far, as they only make sense > when having an ITS. In preparation for that emulate those MMIO > accesses by storing the 64-bit data written into it into a variable > which we later read in the ITS emulation. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > include/kvm/arm_vgic.h | 8 ++++++++ > virt/kvm/arm/vgic-v3-emul.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ > virt/kvm/arm/vgic.c | 35 +++++++++++++++++++++++++++++++++++ > virt/kvm/arm/vgic.h | 4 ++++ > 4 files changed, 91 insertions(+) > > diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > index 3ee063b..8c6cb0e 100644 > --- a/include/kvm/arm_vgic.h > +++ b/include/kvm/arm_vgic.h > @@ -256,6 +256,14 @@ struct vgic_dist { > struct vgic_vm_ops vm_ops; > struct vgic_io_device dist_iodev; > struct vgic_io_device *redist_iodevs; > + > + /* Address of LPI configuration table shared by all redistributors */ > + u64 propbaser; > + > + /* Addresses of LPI pending tables per redistributor */ > + u64 *pendbaser; > + > + bool lpis_enabled; > }; > > struct vgic_v2_cpu_if { > diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c > index a8cf669..5269ad1 100644 > --- a/virt/kvm/arm/vgic-v3-emul.c > +++ b/virt/kvm/arm/vgic-v3-emul.c > @@ -651,6 +651,38 @@ static bool handle_mmio_cfg_reg_redist(struct kvm_vcpu *vcpu, > return vgic_handle_cfg_reg(reg, mmio, offset); > } > > +/* We don't trigger any actions here, just store the register value */ > +static bool handle_mmio_propbaser_redist(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset) > +{ > + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; > + int mode = ACCESS_READ_VALUE; > + > + /* Storing a value with LPIs already enabled is undefined */ > + mode |= dist->lpis_enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; > + vgic_handle_base_register(vcpu, mmio, offset, &dist->propbaser, mode); > + > + return false; > +} > + > +/* We don't trigger any actions here, just store the register value */ > +static bool handle_mmio_pendbaser_redist(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset) > +{ > + struct kvm_vcpu *rdvcpu = mmio->private; > + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; > + int mode = ACCESS_READ_VALUE; > + > + /* Storing a value with LPIs already enabled is undefined */ > + mode |= dist->lpis_enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; > + vgic_handle_base_register(vcpu, mmio, offset, > + &dist->pendbaser[rdvcpu->vcpu_id], mode); > + > + return false; > +} > + > #define SGI_base(x) ((x) + SZ_64K) > > static const struct vgic_io_range vgic_redist_ranges[] = { > @@ -679,6 +711,18 @@ static const struct vgic_io_range vgic_redist_ranges[] = { > .handle_mmio = handle_mmio_raz_wi, > }, > { > + .base = GICR_PENDBASER, > + .len = 0x08, > + .bits_per_irq = 0, > + .handle_mmio = handle_mmio_pendbaser_redist, > + }, > + { > + .base = GICR_PROPBASER, > + .len = 0x08, > + .bits_per_irq = 0, > + .handle_mmio = handle_mmio_propbaser_redist, > + }, > + { > .base = GICR_IDREGS, > .len = 0x30, > .bits_per_irq = 0, > diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c > index 15e447f..49ee92b 100644 > --- a/virt/kvm/arm/vgic.c > +++ b/virt/kvm/arm/vgic.c > @@ -446,6 +446,41 @@ void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, > } > } > > +/* handle a 64-bit register access */ > +void vgic_handle_base_register(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset, u64 *basereg, > + int mode) > +{ why do we have vcpu in the proto? I don't see it used. Also if it were can't we fetch it from mmio->private? why not renaming this into something like vgic_reg64_access as par vgic_reg_access 32b flavor above. vgic_handle* usually is the name of the region handler returning bool? > + u32 reg; > + u64 breg; > + > + switch (offset & ~3) { > + case 0x00: > + breg = *basereg; > + reg = lower_32_bits(breg); > + vgic_reg_access(mmio, ®, offset & 3, mode); > + if (mmio->is_write && (mode & ACCESS_WRITE_VALUE)) { > + breg &= GENMASK_ULL(63, 32); > + breg |= reg; > + *basereg = breg; > + } > + break; > + case 0x04: > + breg = *basereg; > + reg = upper_32_bits(breg); > + vgic_reg_access(mmio, ®, offset & 3, mode); > + if (mmio->is_write && (mode & ACCESS_WRITE_VALUE)) { > + breg = lower_32_bits(breg); > + breg |= (u64)reg << 32; > + *basereg = breg; > + } > + break; > + } > +} > + > + > + some spare white lines Best Regards Eric > bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, > phys_addr_t offset) > { > diff --git a/virt/kvm/arm/vgic.h b/virt/kvm/arm/vgic.h > index a093f5c..b2d791c 100644 > --- a/virt/kvm/arm/vgic.h > +++ b/virt/kvm/arm/vgic.h > @@ -71,6 +71,10 @@ void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, > phys_addr_t offset, int mode); > bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, > phys_addr_t offset); > +void vgic_handle_base_register(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset, u64 *basereg, > + int mode); > > static inline > u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) >
WARNING: multiple messages have this Message-ID (diff)
From: eric.auger@linaro.org (Eric Auger) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 07/15] KVM: arm64: handle ITS related GICv3 redistributor registers Date: Thu, 13 Aug 2015 14:17:38 +0200 [thread overview] Message-ID: <55CC8AE2.2070807@linaro.org> (raw) In-Reply-To: <1436538111-4294-8-git-send-email-andre.przywara@arm.com> On 07/10/2015 04:21 PM, Andre Przywara wrote: > In the GICv3 redistributor there are the PENDBASER and PROPBASER > registers which we did not emulate so far, as they only make sense > when having an ITS. In preparation for that emulate those MMIO > accesses by storing the 64-bit data written into it into a variable > which we later read in the ITS emulation. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > include/kvm/arm_vgic.h | 8 ++++++++ > virt/kvm/arm/vgic-v3-emul.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ > virt/kvm/arm/vgic.c | 35 +++++++++++++++++++++++++++++++++++ > virt/kvm/arm/vgic.h | 4 ++++ > 4 files changed, 91 insertions(+) > > diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > index 3ee063b..8c6cb0e 100644 > --- a/include/kvm/arm_vgic.h > +++ b/include/kvm/arm_vgic.h > @@ -256,6 +256,14 @@ struct vgic_dist { > struct vgic_vm_ops vm_ops; > struct vgic_io_device dist_iodev; > struct vgic_io_device *redist_iodevs; > + > + /* Address of LPI configuration table shared by all redistributors */ > + u64 propbaser; > + > + /* Addresses of LPI pending tables per redistributor */ > + u64 *pendbaser; > + > + bool lpis_enabled; > }; > > struct vgic_v2_cpu_if { > diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c > index a8cf669..5269ad1 100644 > --- a/virt/kvm/arm/vgic-v3-emul.c > +++ b/virt/kvm/arm/vgic-v3-emul.c > @@ -651,6 +651,38 @@ static bool handle_mmio_cfg_reg_redist(struct kvm_vcpu *vcpu, > return vgic_handle_cfg_reg(reg, mmio, offset); > } > > +/* We don't trigger any actions here, just store the register value */ > +static bool handle_mmio_propbaser_redist(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset) > +{ > + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; > + int mode = ACCESS_READ_VALUE; > + > + /* Storing a value with LPIs already enabled is undefined */ > + mode |= dist->lpis_enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; > + vgic_handle_base_register(vcpu, mmio, offset, &dist->propbaser, mode); > + > + return false; > +} > + > +/* We don't trigger any actions here, just store the register value */ > +static bool handle_mmio_pendbaser_redist(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset) > +{ > + struct kvm_vcpu *rdvcpu = mmio->private; > + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; > + int mode = ACCESS_READ_VALUE; > + > + /* Storing a value with LPIs already enabled is undefined */ > + mode |= dist->lpis_enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; > + vgic_handle_base_register(vcpu, mmio, offset, > + &dist->pendbaser[rdvcpu->vcpu_id], mode); > + > + return false; > +} > + > #define SGI_base(x) ((x) + SZ_64K) > > static const struct vgic_io_range vgic_redist_ranges[] = { > @@ -679,6 +711,18 @@ static const struct vgic_io_range vgic_redist_ranges[] = { > .handle_mmio = handle_mmio_raz_wi, > }, > { > + .base = GICR_PENDBASER, > + .len = 0x08, > + .bits_per_irq = 0, > + .handle_mmio = handle_mmio_pendbaser_redist, > + }, > + { > + .base = GICR_PROPBASER, > + .len = 0x08, > + .bits_per_irq = 0, > + .handle_mmio = handle_mmio_propbaser_redist, > + }, > + { > .base = GICR_IDREGS, > .len = 0x30, > .bits_per_irq = 0, > diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c > index 15e447f..49ee92b 100644 > --- a/virt/kvm/arm/vgic.c > +++ b/virt/kvm/arm/vgic.c > @@ -446,6 +446,41 @@ void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, > } > } > > +/* handle a 64-bit register access */ > +void vgic_handle_base_register(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset, u64 *basereg, > + int mode) > +{ why do we have vcpu in the proto? I don't see it used. Also if it were can't we fetch it from mmio->private? why not renaming this into something like vgic_reg64_access as par vgic_reg_access 32b flavor above. vgic_handle* usually is the name of the region handler returning bool? > + u32 reg; > + u64 breg; > + > + switch (offset & ~3) { > + case 0x00: > + breg = *basereg; > + reg = lower_32_bits(breg); > + vgic_reg_access(mmio, ®, offset & 3, mode); > + if (mmio->is_write && (mode & ACCESS_WRITE_VALUE)) { > + breg &= GENMASK_ULL(63, 32); > + breg |= reg; > + *basereg = breg; > + } > + break; > + case 0x04: > + breg = *basereg; > + reg = upper_32_bits(breg); > + vgic_reg_access(mmio, ®, offset & 3, mode); > + if (mmio->is_write && (mode & ACCESS_WRITE_VALUE)) { > + breg = lower_32_bits(breg); > + breg |= (u64)reg << 32; > + *basereg = breg; > + } > + break; > + } > +} > + > + > + some spare white lines Best Regards Eric > bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, > phys_addr_t offset) > { > diff --git a/virt/kvm/arm/vgic.h b/virt/kvm/arm/vgic.h > index a093f5c..b2d791c 100644 > --- a/virt/kvm/arm/vgic.h > +++ b/virt/kvm/arm/vgic.h > @@ -71,6 +71,10 @@ void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, > phys_addr_t offset, int mode); > bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, > phys_addr_t offset); > +void vgic_handle_base_register(struct kvm_vcpu *vcpu, > + struct kvm_exit_mmio *mmio, > + phys_addr_t offset, u64 *basereg, > + int mode); > > static inline > u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) >
next prev parent reply other threads:[~2015-08-13 12:17 UTC|newest] Thread overview: 138+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-07-10 14:21 [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 01/15] KVM: arm/arm64: VGIC: don't track used LRs in the distributor Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-12 9:01 ` Eric Auger 2015-08-12 9:01 ` Eric Auger 2015-08-24 16:33 ` Andre Przywara 2015-08-24 16:33 ` Andre Przywara 2015-08-31 8:42 ` Eric Auger 2015-08-31 8:42 ` Eric Auger 2015-09-02 9:00 ` Andre Przywara 2015-09-02 9:00 ` Andre Przywara 2015-10-02 9:55 ` Pavel Fedin 2015-10-02 9:55 ` Pavel Fedin 2015-10-02 10:32 ` Andre Przywara 2015-10-02 10:32 ` Andre Przywara 2015-10-02 10:39 ` Pavel Fedin 2015-10-02 10:39 ` Pavel Fedin 2015-10-02 12:39 ` Pavel Fedin 2015-10-02 12:39 ` Pavel Fedin 2015-10-02 12:49 ` Andre Przywara 2015-10-02 12:49 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 02/15] KVM: extend struct kvm_msi to hold a 32-bit device ID Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 03/15] KVM: arm/arm64: add emulation model specific destroy function Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 04/15] KVM: arm/arm64: extend arch CAP checks to allow per-VM capabilities Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-12 12:26 ` Eric Auger 2015-08-12 12:26 ` Eric Auger 2015-07-10 14:21 ` [PATCH v2 05/15] KVM: arm/arm64: make GIC frame address initialization model specific Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-12 13:02 ` Eric Auger 2015-08-12 13:02 ` Eric Auger 2015-08-24 17:24 ` Andre Przywara 2015-08-24 17:24 ` Andre Przywara 2015-08-31 9:31 ` Eric Auger 2015-08-31 9:31 ` Eric Auger 2015-07-10 14:21 ` [PATCH v2 06/15] KVM: arm64: Introduce new MMIO region for the ITS base address Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-13 12:17 ` Eric Auger 2015-08-13 12:17 ` Eric Auger 2015-07-10 14:21 ` [PATCH v2 07/15] KVM: arm64: handle ITS related GICv3 redistributor registers Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-13 12:17 ` Eric Auger [this message] 2015-08-13 12:17 ` Eric Auger 2015-08-24 18:08 ` Andre Przywara 2015-08-24 18:08 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 08/15] KVM: arm64: introduce ITS emulation file with stub functions Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-13 12:48 ` Eric Auger 2015-08-13 12:48 ` Eric Auger 2015-08-25 9:39 ` Andre Przywara 2015-08-25 9:39 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 09/15] KVM: arm64: implement basic ITS register handlers Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-13 15:25 ` Eric Auger 2015-08-13 15:25 ` Eric Auger 2015-08-25 10:23 ` Andre Przywara 2015-08-25 10:23 ` Andre Przywara 2015-10-02 7:51 ` Pavel Fedin 2015-10-02 7:51 ` Pavel Fedin 2015-07-10 14:21 ` [PATCH v2 10/15] KVM: arm64: add data structures to model ITS interrupt translation Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-13 15:46 ` Eric Auger 2015-08-13 15:46 ` Eric Auger 2015-08-25 11:15 ` Andre Przywara 2015-08-25 11:15 ` Andre Przywara 2015-08-27 14:16 ` Eric Auger 2015-08-27 14:16 ` Eric Auger 2015-07-10 14:21 ` [PATCH v2 11/15] KVM: arm64: handle pending bit for LPIs in ITS emulation Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-14 11:58 ` Eric Auger 2015-08-14 11:58 ` Eric Auger 2015-08-25 14:34 ` Andre Przywara 2015-08-25 14:34 ` Andre Przywara 2015-08-31 9:45 ` Eric Auger 2015-08-31 9:45 ` Eric Auger 2015-10-07 8:39 ` Pavel Fedin 2015-10-07 8:39 ` Pavel Fedin 2015-10-07 19:53 ` Christoffer Dall 2015-10-07 19:53 ` Christoffer Dall 2015-07-10 14:21 ` [PATCH v2 12/15] KVM: arm64: sync LPI configuration and pending tables Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-14 11:58 ` Eric Auger 2015-08-14 11:58 ` Eric Auger 2015-08-14 12:35 ` Eric Auger 2015-08-14 12:35 ` Eric Auger 2015-08-25 15:47 ` Andre Przywara 2015-08-25 15:47 ` Andre Przywara 2015-08-31 9:51 ` Eric Auger 2015-08-31 9:51 ` Eric Auger 2015-08-25 15:27 ` Andre Przywara 2015-08-25 15:27 ` Andre Przywara 2015-08-31 9:47 ` Eric Auger 2015-08-31 9:47 ` Eric Auger 2015-07-10 14:21 ` [PATCH v2 13/15] KVM: arm64: implement ITS command queue command handlers Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-08-17 13:33 ` Eric Auger 2015-08-17 13:33 ` Eric Auger 2015-10-07 14:54 ` Andre Przywara 2015-10-07 14:54 ` Andre Przywara 2015-07-10 14:21 ` [PATCH v2 14/15] KVM: arm64: implement MSI injection in ITS emulation Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-07-31 13:22 ` Eric Auger 2015-07-31 13:22 ` Eric Auger 2015-08-02 20:20 ` Andre Przywara 2015-08-02 20:20 ` Andre Przywara 2015-08-03 6:41 ` Pavel Fedin 2015-08-03 6:41 ` Pavel Fedin 2015-08-03 9:07 ` Eric Auger 2015-08-03 9:07 ` Eric Auger 2015-08-03 9:16 ` Pavel Fedin 2015-08-03 9:16 ` Pavel Fedin 2015-08-03 15:37 ` Eric Auger 2015-08-03 15:37 ` Eric Auger 2015-08-03 17:06 ` Marc Zyngier 2015-08-03 17:06 ` Marc Zyngier 2015-08-04 6:53 ` Pavel Fedin 2015-08-04 6:53 ` Pavel Fedin 2015-08-24 14:14 ` Andre Przywara 2015-08-24 14:14 ` Andre Przywara 2015-08-17 13:44 ` Eric Auger 2015-08-17 13:44 ` Eric Auger 2015-07-10 14:21 ` [PATCH v2 15/15] KVM: arm64: enable ITS emulation as a virtual MSI controller Andre Przywara 2015-07-10 14:21 ` Andre Przywara 2015-07-15 9:10 ` Pavel Fedin 2015-07-15 9:10 ` Pavel Fedin 2015-07-15 9:52 ` Andre Przywara 2015-07-15 9:52 ` Andre Przywara 2015-07-15 10:01 ` Pavel Fedin 2015-07-15 10:01 ` Pavel Fedin 2015-07-15 12:02 ` [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation Pavel Fedin 2015-07-15 12:02 ` Pavel Fedin 2015-09-24 11:18 ` Pavel Fedin 2015-09-24 11:18 ` Pavel Fedin 2015-09-24 11:35 ` Andre Przywara 2015-09-24 11:35 ` Andre Przywara
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