From: Marc Zyngier <marc.zyngier@arm.com> To: Shannon Zhao <zhaoshenglong@huawei.com>, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, will.deacon@arm.com, wei@redhat.com, cov@codeaurora.org, shannon.zhao@linaro.org, peter.huangpeng@huawei.com, hangaohuai@huawei.com Subject: Re: [PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register Date: Thu, 07 Jan 2016 10:43:09 +0000 [thread overview] Message-ID: <568E413D.8010701@arm.com> (raw) In-Reply-To: <1450771695-11948-5-git-send-email-zhaoshenglong@huawei.com> On 22/12/15 08:07, Shannon Zhao wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > > Add reset handler which gets host value of PMCR_EL0 and make writable > bits architecturally UNKNOWN except PMCR.E which is zero. Add an access > handler for PMCR. > > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> > --- > arch/arm64/kvm/sys_regs.c | 39 +++++++++++++++++++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index e8bf374..c60047e 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -34,6 +34,7 @@ > #include <asm/kvm_emulate.h> > #include <asm/kvm_host.h> > #include <asm/kvm_mmu.h> > +#include <asm/pmu.h> > > #include <trace/events/kvm.h> > > @@ -439,6 +440,40 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr; > } > > +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > +{ > + u64 pmcr, val; > + > + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr)); > + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN > + * except PMCR.E resetting to zero. > + */ > + val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad)) > + & (~ARMV8_PMCR_E); > + vcpu_sys_reg(vcpu, r->reg) = val; > +} > + > +static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 val; > + > + if (p->is_write) { > + /* Only update writeable bits of PMCR */ > + val = vcpu_sys_reg(vcpu, r->reg); > + val &= ~ARMV8_PMCR_MASK; > + val |= p->regval & ARMV8_PMCR_MASK; > + vcpu_sys_reg(vcpu, r->reg) = val; > + } else { > + /* PMCR.P & PMCR.C are RAZ */ > + val = vcpu_sys_reg(vcpu, r->reg) > + & ~(ARMV8_PMCR_P | ARMV8_PMCR_C); > + p->regval = val; > + } How can that work for 32bit, where r->reg is not populated from the trap table? You *know* that you are accessing PMCR, so just use PMCR_EL0 as an index into vcpu_sys_reg() in all cases. You can then drop PMCR_EL0 from the 64bit trap table entry. > + > + return true; > +} > + > /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ > #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ > /* DBGBVRn_EL1 */ \ > @@ -623,7 +658,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > > /* PMCR_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000), > - trap_raz_wi }, > + access_pmcr, reset_pmcr, PMCR_EL0, }, > /* PMCNTENSET_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), > trap_raz_wi }, > @@ -885,7 +920,7 @@ static const struct sys_reg_desc cp15_regs[] = { > { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, > > /* PMU */ > - { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi }, > + { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, > { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, > { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, > { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, > Thanks, M. -- Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register Date: Thu, 07 Jan 2016 10:43:09 +0000 [thread overview] Message-ID: <568E413D.8010701@arm.com> (raw) In-Reply-To: <1450771695-11948-5-git-send-email-zhaoshenglong@huawei.com> On 22/12/15 08:07, Shannon Zhao wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > > Add reset handler which gets host value of PMCR_EL0 and make writable > bits architecturally UNKNOWN except PMCR.E which is zero. Add an access > handler for PMCR. > > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> > --- > arch/arm64/kvm/sys_regs.c | 39 +++++++++++++++++++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index e8bf374..c60047e 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -34,6 +34,7 @@ > #include <asm/kvm_emulate.h> > #include <asm/kvm_host.h> > #include <asm/kvm_mmu.h> > +#include <asm/pmu.h> > > #include <trace/events/kvm.h> > > @@ -439,6 +440,40 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr; > } > > +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > +{ > + u64 pmcr, val; > + > + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr)); > + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN > + * except PMCR.E resetting to zero. > + */ > + val = ((pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad)) > + & (~ARMV8_PMCR_E); > + vcpu_sys_reg(vcpu, r->reg) = val; > +} > + > +static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 val; > + > + if (p->is_write) { > + /* Only update writeable bits of PMCR */ > + val = vcpu_sys_reg(vcpu, r->reg); > + val &= ~ARMV8_PMCR_MASK; > + val |= p->regval & ARMV8_PMCR_MASK; > + vcpu_sys_reg(vcpu, r->reg) = val; > + } else { > + /* PMCR.P & PMCR.C are RAZ */ > + val = vcpu_sys_reg(vcpu, r->reg) > + & ~(ARMV8_PMCR_P | ARMV8_PMCR_C); > + p->regval = val; > + } How can that work for 32bit, where r->reg is not populated from the trap table? You *know* that you are accessing PMCR, so just use PMCR_EL0 as an index into vcpu_sys_reg() in all cases. You can then drop PMCR_EL0 from the 64bit trap table entry. > + > + return true; > +} > + > /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ > #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ > /* DBGBVRn_EL1 */ \ > @@ -623,7 +658,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > > /* PMCR_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000), > - trap_raz_wi }, > + access_pmcr, reset_pmcr, PMCR_EL0, }, > /* PMCNTENSET_EL0 */ > { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), > trap_raz_wi }, > @@ -885,7 +920,7 @@ static const struct sys_reg_desc cp15_regs[] = { > { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, > > /* PMU */ > - { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi }, > + { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, > { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, > { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, > { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, > Thanks, M. -- Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-01-07 10:43 UTC|newest] Thread overview: 197+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-12-22 8:07 [PATCH v8 00/20] KVM: ARM64: Add guest PMU support Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2015-12-22 8:07 ` [PATCH v8 01/20] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2016-01-07 10:20 ` Marc Zyngier 2016-01-07 10:20 ` Marc Zyngier 2015-12-22 8:07 ` [PATCH v8 02/20] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2016-01-07 10:21 ` Marc Zyngier 2016-01-07 10:21 ` Marc Zyngier 2016-01-07 19:07 ` Andrew Jones 2016-01-07 19:07 ` Andrew Jones 2015-12-22 8:07 ` [PATCH v8 03/20] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2016-01-07 10:23 ` Marc Zyngier 2016-01-07 10:23 ` Marc Zyngier 2015-12-22 8:07 ` [PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2015-12-22 8:07 ` Shannon Zhao 2016-01-07 10:43 ` Marc Zyngier [this message] 2016-01-07 10:43 ` Marc Zyngier 2016-01-07 11:16 ` Shannon Zhao 2016-01-07 11:16 ` Shannon Zhao 2016-01-07 11:16 ` Shannon Zhao 2015-12-22 8:08 ` [PATCH v8 05/20] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 10:43 ` Marc Zyngier 2016-01-07 10:43 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 06/20] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 10:44 ` Marc Zyngier 2016-01-07 10:44 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 10:55 ` Marc Zyngier 2016-01-07 10:55 ` Marc Zyngier 2016-01-07 13:48 ` Marc Zyngier 2016-01-07 13:48 ` Marc Zyngier 2016-01-07 14:00 ` Shannon Zhao 2016-01-07 14:00 ` Shannon Zhao 2016-01-07 14:00 ` Shannon Zhao 2015-12-22 8:08 ` [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:03 ` Marc Zyngier 2016-01-07 11:03 ` Marc Zyngier 2016-01-07 11:11 ` Shannon Zhao 2016-01-07 11:11 ` Shannon Zhao 2016-01-07 11:11 ` Shannon Zhao 2016-01-07 12:36 ` Shannon Zhao 2016-01-07 12:36 ` Shannon Zhao 2016-01-07 12:36 ` Shannon Zhao 2016-01-07 13:15 ` Marc Zyngier 2016-01-07 13:15 ` Marc Zyngier 2016-01-07 12:09 ` Shannon Zhao 2016-01-07 12:09 ` Shannon Zhao 2016-01-07 12:09 ` Shannon Zhao 2016-01-07 13:01 ` Marc Zyngier 2016-01-07 13:01 ` Marc Zyngier 2016-01-07 19:17 ` Andrew Jones 2016-01-07 19:17 ` Andrew Jones 2015-12-22 8:08 ` [PATCH v8 09/20] KVM: ARM64: Add access handler for event counter register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:06 ` Marc Zyngier 2016-01-07 11:06 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 10/20] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:09 ` Marc Zyngier 2016-01-07 11:09 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 11/20] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:13 ` Marc Zyngier 2016-01-07 11:13 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 12/20] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:14 ` Marc Zyngier 2016-01-07 11:14 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 13/20] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:29 ` Marc Zyngier 2016-01-07 11:29 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 14/20] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 11:59 ` Marc Zyngier 2016-01-07 11:59 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 15/20] KVM: ARM64: Add a helper to forward trap to guest EL1 Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` [PATCH v8 16/20] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 10:14 ` Marc Zyngier 2016-01-07 10:14 ` Marc Zyngier 2016-01-07 11:15 ` Shannon Zhao 2016-01-07 11:15 ` Shannon Zhao 2016-01-07 11:15 ` Shannon Zhao 2015-12-22 8:08 ` [PATCH v8 17/20] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 13:28 ` Marc Zyngier 2016-01-07 13:28 ` Marc Zyngier 2016-01-07 13:28 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 18/20] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 13:39 ` Marc Zyngier 2016-01-07 13:39 ` Marc Zyngier 2016-01-07 13:39 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 13:51 ` Marc Zyngier 2016-01-07 13:51 ` Marc Zyngier 2015-12-22 8:08 ` [PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2015-12-22 8:08 ` Shannon Zhao 2016-01-07 13:56 ` Marc Zyngier 2016-01-07 13:56 ` Marc Zyngier 2016-01-07 14:35 ` Shannon Zhao 2016-01-07 14:35 ` Shannon Zhao 2016-01-07 14:35 ` Shannon Zhao 2016-01-07 14:36 ` Peter Maydell 2016-01-07 14:36 ` Peter Maydell 2016-01-07 14:49 ` Shannon Zhao 2016-01-07 14:49 ` Shannon Zhao 2016-01-07 14:56 ` Peter Maydell 2016-01-07 14:56 ` Peter Maydell 2016-01-07 20:36 ` Andrew Jones 2016-01-07 20:36 ` Andrew Jones 2016-01-09 12:29 ` Christoffer Dall 2016-01-09 12:29 ` Christoffer Dall 2016-01-09 15:03 ` Marc Zyngier 2016-01-09 15:03 ` Marc Zyngier 2016-01-11 8:45 ` Shannon Zhao 2016-01-11 8:45 ` Shannon Zhao 2016-01-11 8:59 ` Marc Zyngier 2016-01-11 8:59 ` Marc Zyngier 2016-01-11 11:52 ` Andrew Jones 2016-01-11 11:52 ` Andrew Jones 2016-01-11 12:03 ` Shannon Zhao 2016-01-11 12:03 ` Shannon Zhao 2016-01-11 14:07 ` Andrew Jones 2016-01-11 14:07 ` Andrew Jones 2016-01-11 15:09 ` Christoffer Dall 2016-01-11 15:09 ` Christoffer Dall 2016-01-11 16:09 ` Andrew Jones 2016-01-11 16:09 ` Andrew Jones 2016-01-11 16:13 ` Peter Maydell 2016-01-11 16:13 ` Peter Maydell 2016-01-11 16:48 ` Andrew Jones 2016-01-11 16:48 ` Andrew Jones 2016-01-11 16:21 ` Andrew Jones 2016-01-11 16:21 ` Andrew Jones 2016-01-11 16:29 ` Peter Maydell 2016-01-11 16:29 ` Peter Maydell 2016-01-11 16:44 ` Andrew Jones 2016-01-11 16:44 ` Andrew Jones 2016-01-08 3:06 ` Shannon Zhao 2016-01-08 3:06 ` Shannon Zhao 2016-01-08 10:24 ` Peter Maydell 2016-01-08 10:24 ` Peter Maydell 2016-01-08 12:15 ` Shannon Zhao 2016-01-08 12:15 ` Shannon Zhao 2016-01-08 12:56 ` Peter Maydell 2016-01-08 12:56 ` Peter Maydell 2016-01-08 13:31 ` Shannon Zhao 2016-01-08 13:31 ` Shannon Zhao 2016-01-07 20:18 ` Andrew Jones 2016-01-07 20:18 ` Andrew Jones 2016-01-08 2:53 ` Shannon Zhao 2016-01-08 2:53 ` Shannon Zhao 2016-01-08 2:53 ` Shannon Zhao 2016-01-08 11:22 ` Andrew Jones 2016-01-08 11:22 ` Andrew Jones 2016-01-08 15:20 ` Andrew Jones 2016-01-08 15:20 ` Andrew Jones 2016-01-08 15:59 ` Andrew Jones 2016-01-08 15:59 ` Andrew Jones 2016-01-07 14:10 ` [PATCH v8 00/20] KVM: ARM64: Add guest PMU support Marc Zyngier 2016-01-07 14:10 ` Marc Zyngier 2016-01-07 14:12 ` Will Deacon 2016-01-07 14:12 ` Will Deacon 2016-01-07 14:21 ` Marc Zyngier 2016-01-07 14:21 ` Marc Zyngier
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