From: Weiwei Li <liweiwei@iscas.ac.cn> To: Anup Patel <anup@brainfault.org> Cc: "Wei Wu (吴伟)" <lazyparser@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, wangjunqiang@iscas.ac.cn, "Bin Meng" <bin.meng@windriver.com>, "QEMU Developers" <qemu-devel@nongnu.org>, "Alistair Francis" <alistair.francis@wdc.com>, "Palmer Dabbelt" <palmer@dabbelt.com> Subject: Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension Date: Tue, 18 Jan 2022 16:32:14 +0800 [thread overview] Message-ID: <57d51f70-2add-5383-6062-eb6f661394b7@iscas.ac.cn> (raw) In-Reply-To: <CAAhSdy3C7eNcrq2WJ_u7GnY-z=MJQCVQXL=iKufFETswzZ0awQ@mail.gmail.com> 在 2022/1/18 上午11:32, Anup Patel 写道: > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - add PTE_N bit >> - add PTE_N bit check for inner PTE >> - update address translation to support 64KiB continuous region (napot_bits = 4) >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> Cc: Anup Patel <anup@brainfault.org> > I did review this patch previously. > > In any case, this looks good to me. > > Reviewed-by: Anup Patel <anup@brainfault.org> > > Regards, > Anup Thanks a lot. Sorry for your repeated work. Regards. Weiwei Li >> --- >> target/riscv/cpu.c | 2 ++ >> target/riscv/cpu.h | 1 + >> target/riscv/cpu_bits.h | 1 + >> target/riscv/cpu_helper.c | 18 +++++++++++++++--- >> 4 files changed, 19 insertions(+), 3 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 9bc25d3055..ff6c86c85b 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = { >> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), >> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), >> >> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), >> + >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 4d63086765..d3d17cde82 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -327,6 +327,7 @@ struct RISCVCPU { >> bool ext_counters; >> bool ext_ifencei; >> bool ext_icsr; >> + bool ext_svnapot; >> bool ext_zfh; >> bool ext_zfhmin; >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index 282cd8eecd..5501e9698b 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -486,6 +486,7 @@ typedef enum { >> #define PTE_A 0x040 /* Accessed */ >> #define PTE_D 0x080 /* Dirty */ >> #define PTE_SOFT 0x300 /* Reserved for Software */ >> +#define PTE_N 0x8000000000000000 /* NAPOT translation */ >> >> /* Page table PPN shift amount */ >> #define PTE_PPN_SHIFT 10 >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index 1820188f41..c276760c7f 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -621,12 +621,13 @@ restart: >> >> hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT; >> >> + RISCVCPU *cpu = env_archcpu(env); >> if (!(pte & PTE_V)) { >> /* Invalid PTE */ >> return TRANSLATE_FAIL; >> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { >> /* Inner PTE, continue walking */ >> - if (pte & (PTE_D | PTE_A | PTE_U)) { >> + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { >> return TRANSLATE_FAIL; >> } >> base = ppn << PGSHIFT; >> @@ -702,8 +703,19 @@ restart: >> /* for superpage mappings, make a fake leaf PTE for the TLB's >> benefit. */ >> target_ulong vpn = addr >> PGSHIFT; >> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | >> - (addr & ~TARGET_PAGE_MASK); >> + >> + int napot_bits = 0; >> + if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) { >> + napot_bits = ctzl(ppn) + 1; >> + if ((i != (levels - 1)) || (napot_bits != 4)) { >> + return TRANSLATE_FAIL; >> + } >> + } >> + >> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) | >> + (vpn & (((target_ulong)1 << napot_bits) - 1)) | >> + (vpn & (((target_ulong)1 << ptshift) - 1)) >> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); >> >> /* set permissions on the TLB entry */ >> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { >> -- >> 2.17.1 >>
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: Anup Patel <anup@brainfault.org> Cc: "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "QEMU Developers" <qemu-devel@nongnu.org>, wangjunqiang@iscas.ac.cn, "Wei Wu (吴伟)" <lazyparser@gmail.com> Subject: Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension Date: Tue, 18 Jan 2022 16:32:14 +0800 [thread overview] Message-ID: <57d51f70-2add-5383-6062-eb6f661394b7@iscas.ac.cn> (raw) In-Reply-To: <CAAhSdy3C7eNcrq2WJ_u7GnY-z=MJQCVQXL=iKufFETswzZ0awQ@mail.gmail.com> 在 2022/1/18 上午11:32, Anup Patel 写道: > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - add PTE_N bit >> - add PTE_N bit check for inner PTE >> - update address translation to support 64KiB continuous region (napot_bits = 4) >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> Cc: Anup Patel <anup@brainfault.org> > I did review this patch previously. > > In any case, this looks good to me. > > Reviewed-by: Anup Patel <anup@brainfault.org> > > Regards, > Anup Thanks a lot. Sorry for your repeated work. Regards. Weiwei Li >> --- >> target/riscv/cpu.c | 2 ++ >> target/riscv/cpu.h | 1 + >> target/riscv/cpu_bits.h | 1 + >> target/riscv/cpu_helper.c | 18 +++++++++++++++--- >> 4 files changed, 19 insertions(+), 3 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 9bc25d3055..ff6c86c85b 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = { >> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), >> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), >> >> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), >> + >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 4d63086765..d3d17cde82 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -327,6 +327,7 @@ struct RISCVCPU { >> bool ext_counters; >> bool ext_ifencei; >> bool ext_icsr; >> + bool ext_svnapot; >> bool ext_zfh; >> bool ext_zfhmin; >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index 282cd8eecd..5501e9698b 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -486,6 +486,7 @@ typedef enum { >> #define PTE_A 0x040 /* Accessed */ >> #define PTE_D 0x080 /* Dirty */ >> #define PTE_SOFT 0x300 /* Reserved for Software */ >> +#define PTE_N 0x8000000000000000 /* NAPOT translation */ >> >> /* Page table PPN shift amount */ >> #define PTE_PPN_SHIFT 10 >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index 1820188f41..c276760c7f 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -621,12 +621,13 @@ restart: >> >> hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT; >> >> + RISCVCPU *cpu = env_archcpu(env); >> if (!(pte & PTE_V)) { >> /* Invalid PTE */ >> return TRANSLATE_FAIL; >> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { >> /* Inner PTE, continue walking */ >> - if (pte & (PTE_D | PTE_A | PTE_U)) { >> + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { >> return TRANSLATE_FAIL; >> } >> base = ppn << PGSHIFT; >> @@ -702,8 +703,19 @@ restart: >> /* for superpage mappings, make a fake leaf PTE for the TLB's >> benefit. */ >> target_ulong vpn = addr >> PGSHIFT; >> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | >> - (addr & ~TARGET_PAGE_MASK); >> + >> + int napot_bits = 0; >> + if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) { >> + napot_bits = ctzl(ppn) + 1; >> + if ((i != (levels - 1)) || (napot_bits != 4)) { >> + return TRANSLATE_FAIL; >> + } >> + } >> + >> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) | >> + (vpn & (((target_ulong)1 << napot_bits) - 1)) | >> + (vpn & (((target_ulong)1 << ptshift) - 1)) >> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); >> >> /* set permissions on the TLB entry */ >> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { >> -- >> 2.17.1 >>
next prev parent reply other threads:[~2022-01-18 8:37 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-18 1:17 [PATCH v5 0/5] support subsets of virtual memory extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li 2022-01-18 3:30 ` Anup Patel 2022-01-18 3:30 ` Anup Patel 2022-01-18 4:51 ` Alistair Francis 2022-01-18 4:51 ` Alistair Francis 2022-01-18 11:54 ` Guo Ren 2022-01-18 11:54 ` Guo Ren 2022-01-20 13:47 ` Guo Ren 2022-01-20 22:28 ` LIU Zhiwei 2022-01-21 1:50 ` Guo Ren 2022-01-21 1:50 ` Guo Ren 2022-01-21 2:08 ` LIU Zhiwei 2022-01-21 2:08 ` LIU Zhiwei 2022-01-18 8:33 ` Guo Ren 2022-01-18 8:33 ` Guo Ren 2022-01-18 8:51 ` Anup Patel 2022-01-18 8:51 ` Anup Patel 2022-01-18 11:15 ` Guo Ren 2022-01-18 11:15 ` Guo Ren 2022-01-18 11:25 ` Anup Patel 2022-01-18 11:25 ` Anup Patel 2022-01-18 11:28 ` Anup Patel 2022-01-18 11:28 ` Anup Patel 2022-01-18 11:57 ` Guo Ren 2022-01-18 11:57 ` Guo Ren 2022-01-18 11:29 ` Weiwei Li 2022-01-18 11:29 ` Weiwei Li 2022-01-19 3:14 ` LIU Zhiwei 2022-01-18 1:17 ` [PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 3/5] target/riscv: add support for svnapot extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 3:32 ` Anup Patel 2022-01-18 3:32 ` Anup Patel 2022-01-18 8:32 ` Weiwei Li [this message] 2022-01-18 8:32 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 4/5] target/riscv: add support for svinval extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 5/5] target/riscv: add support for svpbmt extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 3:35 ` Anup Patel 2022-01-18 3:35 ` Anup Patel 2022-01-18 8:33 ` Weiwei Li 2022-01-18 8:33 ` Weiwei Li 2022-01-18 9:09 ` Weiwei Li 2022-01-18 9:09 ` Weiwei Li 2022-01-18 11:04 ` Anup Patel 2022-01-18 11:04 ` Anup Patel 2022-01-18 11:21 ` Weiwei Li 2022-01-18 11:21 ` Weiwei Li
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