From: Weiwei Li <liweiwei@iscas.ac.cn> To: Anup Patel <anup@brainfault.org> Cc: "Wei Wu (吴伟)" <lazyparser@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "Heiko Stuebner" <heiko@sntech.de>, wangjunqiang@iscas.ac.cn, "Bin Meng" <bin.meng@windriver.com>, "QEMU Developers" <qemu-devel@nongnu.org>, "Alistair Francis" <alistair.francis@wdc.com>, "Palmer Dabbelt" <palmer@dabbelt.com> Subject: Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension Date: Tue, 18 Jan 2022 16:33:28 +0800 [thread overview] Message-ID: <9f4821ae-b688-c908-7f93-6f4daed2554a@iscas.ac.cn> (raw) In-Reply-To: <CAAhSdy3bMG3htJSCMsT9HjrYXQP5XZk8y_8KN7pXjPoNPzc58w@mail.gmail.com> 在 2022/1/18 上午11:35, Anup Patel 写道: > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently >> - add PTE_PBMT bit check for inner PTE >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> Cc: Heiko Stuebner <heiko@sntech.de> >> Cc: Anup Patel <anup@brainfault.org> >> --- >> target/riscv/cpu.c | 1 + >> target/riscv/cpu.h | 1 + >> target/riscv/cpu_bits.h | 2 ++ >> target/riscv/cpu_helper.c | 4 +++- >> 4 files changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 45ac98e06b..4f82bd00a3 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { >> >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), >> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), >> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), >> >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index c3d1845ca1..53f314c752 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -329,6 +329,7 @@ struct RISCVCPU { >> bool ext_icsr; >> bool ext_svinval; >> bool ext_svnapot; >> + bool ext_svpbmt; >> bool ext_zfh; >> bool ext_zfhmin; >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index 5501e9698b..24b7eb2b1f 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -486,7 +486,9 @@ typedef enum { >> #define PTE_A 0x040 /* Accessed */ >> #define PTE_D 0x080 /* Dirty */ >> #define PTE_SOFT 0x300 /* Reserved for Software */ >> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ >> #define PTE_N 0x8000000000000000 /* NAPOT translation */ >> +#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ >> >> /* Page table PPN shift amount */ >> #define PTE_PPN_SHIFT 10 >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index c276760c7f..9fffaccffb 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -625,9 +625,11 @@ restart: >> if (!(pte & PTE_V)) { >> /* Invalid PTE */ >> return TRANSLATE_FAIL; >> + } else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT)) { > Rather than, type-casting defines here you can simply define > ULL constants. E.g. > #define PTE_PBMT 0x6000000000000000ULL OK. I'll update this. Regards, Weiwei Li >> + return TRANSLATE_FAIL; >> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { >> /* Inner PTE, continue walking */ >> - if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { >> + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) { >> return TRANSLATE_FAIL; >> } >> base = ppn << PGSHIFT; >> -- >> 2.17.1 >> > Regards, > Anup
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: Anup Patel <anup@brainfault.org> Cc: "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "QEMU Developers" <qemu-devel@nongnu.org>, wangjunqiang@iscas.ac.cn, "Wei Wu (吴伟)" <lazyparser@gmail.com>, "Heiko Stuebner" <heiko@sntech.de> Subject: Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension Date: Tue, 18 Jan 2022 16:33:28 +0800 [thread overview] Message-ID: <9f4821ae-b688-c908-7f93-6f4daed2554a@iscas.ac.cn> (raw) In-Reply-To: <CAAhSdy3bMG3htJSCMsT9HjrYXQP5XZk8y_8KN7pXjPoNPzc58w@mail.gmail.com> 在 2022/1/18 上午11:35, Anup Patel 写道: > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently >> - add PTE_PBMT bit check for inner PTE >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> Cc: Heiko Stuebner <heiko@sntech.de> >> Cc: Anup Patel <anup@brainfault.org> >> --- >> target/riscv/cpu.c | 1 + >> target/riscv/cpu.h | 1 + >> target/riscv/cpu_bits.h | 2 ++ >> target/riscv/cpu_helper.c | 4 +++- >> 4 files changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 45ac98e06b..4f82bd00a3 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = { >> >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), >> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), >> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), >> >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index c3d1845ca1..53f314c752 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -329,6 +329,7 @@ struct RISCVCPU { >> bool ext_icsr; >> bool ext_svinval; >> bool ext_svnapot; >> + bool ext_svpbmt; >> bool ext_zfh; >> bool ext_zfhmin; >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index 5501e9698b..24b7eb2b1f 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -486,7 +486,9 @@ typedef enum { >> #define PTE_A 0x040 /* Accessed */ >> #define PTE_D 0x080 /* Dirty */ >> #define PTE_SOFT 0x300 /* Reserved for Software */ >> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ >> #define PTE_N 0x8000000000000000 /* NAPOT translation */ >> +#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ >> >> /* Page table PPN shift amount */ >> #define PTE_PPN_SHIFT 10 >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >> index c276760c7f..9fffaccffb 100644 >> --- a/target/riscv/cpu_helper.c >> +++ b/target/riscv/cpu_helper.c >> @@ -625,9 +625,11 @@ restart: >> if (!(pte & PTE_V)) { >> /* Invalid PTE */ >> return TRANSLATE_FAIL; >> + } else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT)) { > Rather than, type-casting defines here you can simply define > ULL constants. E.g. > #define PTE_PBMT 0x6000000000000000ULL OK. I'll update this. Regards, Weiwei Li >> + return TRANSLATE_FAIL; >> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { >> /* Inner PTE, continue walking */ >> - if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) { >> + if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) { >> return TRANSLATE_FAIL; >> } >> base = ppn << PGSHIFT; >> -- >> 2.17.1 >> > Regards, > Anup
next prev parent reply other threads:[~2022-01-18 8:49 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-18 1:17 [PATCH v5 0/5] support subsets of virtual memory extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li 2022-01-18 3:30 ` Anup Patel 2022-01-18 3:30 ` Anup Patel 2022-01-18 4:51 ` Alistair Francis 2022-01-18 4:51 ` Alistair Francis 2022-01-18 11:54 ` Guo Ren 2022-01-18 11:54 ` Guo Ren 2022-01-20 13:47 ` Guo Ren 2022-01-20 22:28 ` LIU Zhiwei 2022-01-21 1:50 ` Guo Ren 2022-01-21 1:50 ` Guo Ren 2022-01-21 2:08 ` LIU Zhiwei 2022-01-21 2:08 ` LIU Zhiwei 2022-01-18 8:33 ` Guo Ren 2022-01-18 8:33 ` Guo Ren 2022-01-18 8:51 ` Anup Patel 2022-01-18 8:51 ` Anup Patel 2022-01-18 11:15 ` Guo Ren 2022-01-18 11:15 ` Guo Ren 2022-01-18 11:25 ` Anup Patel 2022-01-18 11:25 ` Anup Patel 2022-01-18 11:28 ` Anup Patel 2022-01-18 11:28 ` Anup Patel 2022-01-18 11:57 ` Guo Ren 2022-01-18 11:57 ` Guo Ren 2022-01-18 11:29 ` Weiwei Li 2022-01-18 11:29 ` Weiwei Li 2022-01-19 3:14 ` LIU Zhiwei 2022-01-18 1:17 ` [PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 3/5] target/riscv: add support for svnapot extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 3:32 ` Anup Patel 2022-01-18 3:32 ` Anup Patel 2022-01-18 8:32 ` Weiwei Li 2022-01-18 8:32 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 4/5] target/riscv: add support for svinval extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 1:17 ` [PATCH v5 5/5] target/riscv: add support for svpbmt extension Weiwei Li 2022-01-18 1:17 ` Weiwei Li 2022-01-18 3:35 ` Anup Patel 2022-01-18 3:35 ` Anup Patel 2022-01-18 8:33 ` Weiwei Li [this message] 2022-01-18 8:33 ` Weiwei Li 2022-01-18 9:09 ` Weiwei Li 2022-01-18 9:09 ` Weiwei Li 2022-01-18 11:04 ` Anup Patel 2022-01-18 11:04 ` Anup Patel 2022-01-18 11:21 ` Weiwei Li 2022-01-18 11:21 ` Weiwei Li
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