From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [Qemu-devel] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension
Date: Fri, 7 Jun 2019 14:56:46 -0700 [thread overview]
Message-ID: <77ba193a34b10576a6f3e6fb9bb63d35b3617732.1559944445.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6111f0f0bc..38583e7a6e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -436,6 +436,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_u) {
target_misa |= RVU;
}
+ if (cpu->cfg.ext_h) {
+ target_misa |= RVH;
+ }
set_misa(env, RVXLEN | target_misa);
}
@@ -472,6 +475,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b3b32dbbc..342e628379 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -259,6 +259,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
+ bool ext_h;
char *priv_spec;
char *user_spec;
--
2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com
Subject: [Qemu-riscv] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension
Date: Fri, 7 Jun 2019 14:56:46 -0700 [thread overview]
Message-ID: <77ba193a34b10576a6f3e6fb9bb63d35b3617732.1559944445.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6111f0f0bc..38583e7a6e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -436,6 +436,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_u) {
target_misa |= RVU;
}
+ if (cpu->cfg.ext_h) {
+ target_misa |= RVH;
+ }
set_misa(env, RVXLEN | target_misa);
}
@@ -472,6 +475,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b3b32dbbc..342e628379 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -259,6 +259,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
+ bool ext_h;
char *priv_spec;
char *user_spec;
--
2.21.0
next prev parent reply other threads:[~2019-06-07 22:21 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-07 21:55 [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 12/27] target/riscv: Add background register swapping function Alistair Francis
2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 25/27] target/riscv: Implement second stage MMU Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis
2019-06-07 21:56 ` Alistair Francis [this message]
2019-06-07 21:56 ` [Qemu-riscv] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-07-15 11:50 ` [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Chih-Min Chao
2019-07-15 11:50 ` [Qemu-riscv] " Chih-Min Chao
2019-07-17 0:13 ` Alistair Francis
2019-07-17 0:13 ` [Qemu-riscv] " Alistair Francis
2019-07-15 11:59 ` Peter Maydell
2019-07-15 11:59 ` [Qemu-riscv] " Peter Maydell
2019-07-17 0:14 ` Alistair Francis
2019-07-17 0:14 ` [Qemu-riscv] " Alistair Francis
2019-07-17 3:55 ` Chih-Min Chao
2019-07-17 3:55 ` [Qemu-riscv] " Chih-Min Chao
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