From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Subject: [Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS Date: Fri, 7 Jun 2019 14:56:11 -0700 [thread overview] Message-ID: <7b1a129161caffc16d473acea53861596d0c3d1e.1559944445.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com> When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_plic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 1e7e4c8d51..25da29fa3d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -147,7 +147,17 @@ static void sifive_plic_update(SiFivePLICState *plic) riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); break; case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + if (riscv_cpu_virt_enabled(env)) { + if (level) { + atomic_or(&env->bsip, MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } else { + atomic_and(&env->bsip, ~MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } + } else { + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + } break; default: break; -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS Date: Fri, 7 Jun 2019 14:56:11 -0700 [thread overview] Message-ID: <7b1a129161caffc16d473acea53861596d0c3d1e.1559944445.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1559944445.git.alistair.francis@wdc.com> When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_plic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 1e7e4c8d51..25da29fa3d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -147,7 +147,17 @@ static void sifive_plic_update(SiFivePLICState *plic) riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); break; case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + if (riscv_cpu_virt_enabled(env)) { + if (level) { + atomic_or(&env->bsip, MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } else { + atomic_and(&env->bsip, ~MIP_SEIP); + g_assert(riscv_cpu_virt_enabled(env)); + } + } else { + riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); + } break; default: break; -- 2.21.0
next prev parent reply other threads:[~2019-06-07 22:18 UTC|newest] Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-07 21:55 [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 04/27] target/riscv: Add the force HS exception mode Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:55 ` [Qemu-devel] [PATCH v1 12/27] target/riscv: Add background register swapping function Alistair Francis 2019-06-07 21:55 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` Alistair Francis [this message] 2019-06-07 21:56 ` [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 19/27] target/riscv: Add hfence instructions Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 25/27] target/riscv: Implement second stage MMU Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-06-07 21:56 ` [Qemu-devel] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis 2019-06-07 21:56 ` [Qemu-riscv] " Alistair Francis 2019-07-15 11:50 ` [Qemu-devel] [PATCH v1 00/27] Add RISC-V Hypervisor Extension Chih-Min Chao 2019-07-15 11:50 ` [Qemu-riscv] " Chih-Min Chao 2019-07-17 0:13 ` Alistair Francis 2019-07-17 0:13 ` [Qemu-riscv] " Alistair Francis 2019-07-15 11:59 ` Peter Maydell 2019-07-15 11:59 ` [Qemu-riscv] " Peter Maydell 2019-07-17 0:14 ` Alistair Francis 2019-07-17 0:14 ` [Qemu-riscv] " Alistair Francis 2019-07-17 3:55 ` Chih-Min Chao 2019-07-17 3:55 ` [Qemu-riscv] " Chih-Min Chao
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