From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Kuogee Hsieh <quic_khsieh@quicinc.com>, dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, airlied@linux.ie, agross@kernel.org, bjorn.andersson@linaro.org Cc: quic_abhinavk@quicinc.com, quic_aravindh@quicinc.com, quic_sbillaka@quicinc.com, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 3/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Date: Thu, 17 Feb 2022 09:46:13 +0300 [thread overview] Message-ID: <82707bbf-5005-9765-292b-1f883a32946c@linaro.org> (raw) In-Reply-To: <1645049106-30481-4-git-send-email-quic_khsieh@quicinc.com> On 17/02/2022 01:05, Kuogee Hsieh wrote: > To improve code readability, this patch replace BIT(x) with > correspond register bit define string > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> This patch should come first. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index b68e696..8f10aab 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -61,6 +61,12 @@ > > #define INTF_MUX 0x25C > > +#define INTF_CFG_ACTIVE_H_EN BIT(29) > +#define INTF_CFG_ACTIVE_V_EN BIT(30) > + > +#define INTF_CFG2_DATABUS_WIDEN BIT(0) > +#define INTF_CFG2_DATA_HCTL_EN BIT(4) > + > static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, > const struct dpu_mdss_cfg *m, > void __iomem *addr, > @@ -139,13 +145,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > > if (active_h_end) { > active_hctl = (active_h_end << 16) | active_h_start; > - intf_cfg |= BIT(29); > + intf_cfg |= INTF_CFG_ACTIVE_H_EN; > } else { > active_hctl = 0; > } > > if (active_v_end) > - intf_cfg |= BIT(30); > + intf_cfg |= INTF_CFG_ACTIVE_V_EN; > > hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; > display_hctl = (hsync_end_x << 16) | hsync_start_x; > @@ -156,7 +162,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > * if compression is enabled in 1 pixel per clock mode > */ > if (p->wide_bus_en) > - intf_cfg2 |= (BIT(0) | BIT(4)); > + intf_cfg2 |= (INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN); > > data_width = p->width; > > @@ -178,8 +184,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > active_hctl = (active_h_end << 16) | active_h_start; > display_hctl = active_hctl; > > - intf_cfg |= BIT(29); > - intf_cfg |= BIT(30); > + intf_cfg |= INTF_CFG_ACTIVE_H_EN; > + intf_cfg |= INTF_CFG_ACTIVE_V_EN; > } > > den_polarity = 0; -- With best wishes Dmitry
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Kuogee Hsieh <quic_khsieh@quicinc.com>, dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, airlied@linux.ie, agross@kernel.org, bjorn.andersson@linaro.org Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org, quic_aravindh@quicinc.com, freedreno@lists.freedesktop.org Subject: Re: [PATCH v7 3/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Date: Thu, 17 Feb 2022 09:46:13 +0300 [thread overview] Message-ID: <82707bbf-5005-9765-292b-1f883a32946c@linaro.org> (raw) In-Reply-To: <1645049106-30481-4-git-send-email-quic_khsieh@quicinc.com> On 17/02/2022 01:05, Kuogee Hsieh wrote: > To improve code readability, this patch replace BIT(x) with > correspond register bit define string > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> This patch should come first. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index b68e696..8f10aab 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -61,6 +61,12 @@ > > #define INTF_MUX 0x25C > > +#define INTF_CFG_ACTIVE_H_EN BIT(29) > +#define INTF_CFG_ACTIVE_V_EN BIT(30) > + > +#define INTF_CFG2_DATABUS_WIDEN BIT(0) > +#define INTF_CFG2_DATA_HCTL_EN BIT(4) > + > static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, > const struct dpu_mdss_cfg *m, > void __iomem *addr, > @@ -139,13 +145,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > > if (active_h_end) { > active_hctl = (active_h_end << 16) | active_h_start; > - intf_cfg |= BIT(29); > + intf_cfg |= INTF_CFG_ACTIVE_H_EN; > } else { > active_hctl = 0; > } > > if (active_v_end) > - intf_cfg |= BIT(30); > + intf_cfg |= INTF_CFG_ACTIVE_V_EN; > > hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; > display_hctl = (hsync_end_x << 16) | hsync_start_x; > @@ -156,7 +162,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > * if compression is enabled in 1 pixel per clock mode > */ > if (p->wide_bus_en) > - intf_cfg2 |= (BIT(0) | BIT(4)); > + intf_cfg2 |= (INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN); > > data_width = p->width; > > @@ -178,8 +184,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > active_hctl = (active_h_end << 16) | active_h_start; > display_hctl = active_hctl; > > - intf_cfg |= BIT(29); > - intf_cfg |= BIT(30); > + intf_cfg |= INTF_CFG_ACTIVE_H_EN; > + intf_cfg |= INTF_CFG_ACTIVE_V_EN; > } > > den_polarity = 0; -- With best wishes Dmitry
next prev parent reply other threads:[~2022-02-17 6:46 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-16 22:05 [PATCH v7 0/2] drm/msm/dp: enable widebus feature base on chip hardware revision Kuogee Hsieh 2022-02-16 22:05 ` Kuogee Hsieh 2022-02-16 22:05 ` [PATCH v7 1/4] drm/msm/dpu: revise timing engine programming to support widebus feature Kuogee Hsieh 2022-02-16 22:05 ` Kuogee Hsieh 2022-02-17 6:34 ` Dmitry Baryshkov 2022-02-17 6:34 ` Dmitry Baryshkov 2022-02-17 20:24 ` Kuogee Hsieh 2022-02-17 20:24 ` Kuogee Hsieh 2022-02-16 22:05 ` [PATCH v7 2/4] drm/msm/dpu: delete DATA_HCTL_EN from sc7280 hw feature Kuogee Hsieh 2022-02-16 22:05 ` Kuogee Hsieh 2022-02-16 22:05 ` [PATCH v7 3/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Kuogee Hsieh 2022-02-16 22:05 ` Kuogee Hsieh 2022-02-17 6:46 ` Dmitry Baryshkov [this message] 2022-02-17 6:46 ` Dmitry Baryshkov 2022-02-16 22:05 ` [PATCH v7 4/4] drm/msm/dp: enable widebus feature for display port Kuogee Hsieh 2022-02-16 22:05 ` Kuogee Hsieh 2022-02-17 6:45 ` Dmitry Baryshkov 2022-02-17 6:45 ` Dmitry Baryshkov
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