From: Steven Price <steven.price@arm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
qemu-devel@nongnu.org, Juan Quintela <quintela@redhat.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Peter Maydell <Peter.Maydell@arm.com>,
Haibo Xu <Haibo.Xu@arm.com>
Subject: Re: [PATCH v2 0/2] MTE support for KVM guest
Date: Thu, 10 Sep 2020 11:24:51 +0100 [thread overview]
Message-ID: <842807ac-562a-36ce-8061-aa323341b605@arm.com> (raw)
In-Reply-To: <8e661984-70bc-790c-8636-39dcd8b00131@linaro.org>
On 10/09/2020 01:33, Richard Henderson wrote:
> On 9/4/20 9:00 AM, Steven Price wrote:
>> 3. Doesn't provide any new methods for the VMM to access the tags on
>> memory.
> ...
>> (3) may be problematic and I'd welcome input from those familiar with
>> VMMs. User space cannot access tags unless the memory is mapped with the
>> PROT_MTE flag. However enabling PROT_MTE will also enable tag checking
>> for the user space process (assuming the VMM enables tag checking for
>> the process)...
>
> The latest version of the kernel patches for user mte support has separate
> controls for how tag check fail is reported. Including
>
>> +- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
>
> That may be less than optimal once userland starts uses tags itself, e.g.
> running qemu itself with an mte-aware malloc.
>
> Independent of that, there's also the TCO bit, which can be toggled by any
> piece of code that wants to disable checking locally.
Yes, I would expect the TCO bit is the best option for wrapping accesses
to make them unchecked.
> However, none of that is required for accessing tags. User space can always
> load/store tags via LDG/STG. That's going to be slow, though.
Yes as things stand LDG/STG is the way for user space to access tags.
Since I don't have any real hardware I can't really comment on speed.
> It's a shame that LDGM/STGM are privileged instructions. I don't understand
> why that was done, since there's absolutely nothing that those insns can do
> that you can't do with (up to) 16x LDG/STG.
It is a shame, however I suspect this is because to use those
instructions you need to know the block size held in GMID_EL1. And at
least in theory that could vary between CPUs.
> I think it might be worth adding some sort of kernel entry point that can bulk
> copy tags, e.g. page aligned quantities. But that's just a speed of migration
> thing and could come later.
When we have some real hardware it would be worth profiling this. At the
moment I've no idea whether the kernel entry overhead would make such an
interface useful from a performance perspective or not.
Steve
WARNING: multiple messages have this Message-ID (diff)
From: Steven Price <steven.price@arm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Peter Maydell <Peter.Maydell@arm.com>,
Haibo Xu <Haibo.Xu@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
qemu-devel@nongnu.org, Juan Quintela <quintela@redhat.com>,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/2] MTE support for KVM guest
Date: Thu, 10 Sep 2020 11:24:51 +0100 [thread overview]
Message-ID: <842807ac-562a-36ce-8061-aa323341b605@arm.com> (raw)
In-Reply-To: <8e661984-70bc-790c-8636-39dcd8b00131@linaro.org>
On 10/09/2020 01:33, Richard Henderson wrote:
> On 9/4/20 9:00 AM, Steven Price wrote:
>> 3. Doesn't provide any new methods for the VMM to access the tags on
>> memory.
> ...
>> (3) may be problematic and I'd welcome input from those familiar with
>> VMMs. User space cannot access tags unless the memory is mapped with the
>> PROT_MTE flag. However enabling PROT_MTE will also enable tag checking
>> for the user space process (assuming the VMM enables tag checking for
>> the process)...
>
> The latest version of the kernel patches for user mte support has separate
> controls for how tag check fail is reported. Including
>
>> +- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
>
> That may be less than optimal once userland starts uses tags itself, e.g.
> running qemu itself with an mte-aware malloc.
>
> Independent of that, there's also the TCO bit, which can be toggled by any
> piece of code that wants to disable checking locally.
Yes, I would expect the TCO bit is the best option for wrapping accesses
to make them unchecked.
> However, none of that is required for accessing tags. User space can always
> load/store tags via LDG/STG. That's going to be slow, though.
Yes as things stand LDG/STG is the way for user space to access tags.
Since I don't have any real hardware I can't really comment on speed.
> It's a shame that LDGM/STGM are privileged instructions. I don't understand
> why that was done, since there's absolutely nothing that those insns can do
> that you can't do with (up to) 16x LDG/STG.
It is a shame, however I suspect this is because to use those
instructions you need to know the block size held in GMID_EL1. And at
least in theory that could vary between CPUs.
> I think it might be worth adding some sort of kernel entry point that can bulk
> copy tags, e.g. page aligned quantities. But that's just a speed of migration
> thing and could come later.
When we have some real hardware it would be worth profiling this. At the
moment I've no idea whether the kernel entry overhead would make such an
interface useful from a performance perspective or not.
Steve
WARNING: multiple messages have this Message-ID (diff)
From: Steven Price <steven.price@arm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>
Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Peter Maydell <Peter.Maydell@arm.com>,
qemu-devel@nongnu.org, Juan Quintela <quintela@redhat.com>,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/2] MTE support for KVM guest
Date: Thu, 10 Sep 2020 11:24:51 +0100 [thread overview]
Message-ID: <842807ac-562a-36ce-8061-aa323341b605@arm.com> (raw)
In-Reply-To: <8e661984-70bc-790c-8636-39dcd8b00131@linaro.org>
On 10/09/2020 01:33, Richard Henderson wrote:
> On 9/4/20 9:00 AM, Steven Price wrote:
>> 3. Doesn't provide any new methods for the VMM to access the tags on
>> memory.
> ...
>> (3) may be problematic and I'd welcome input from those familiar with
>> VMMs. User space cannot access tags unless the memory is mapped with the
>> PROT_MTE flag. However enabling PROT_MTE will also enable tag checking
>> for the user space process (assuming the VMM enables tag checking for
>> the process)...
>
> The latest version of the kernel patches for user mte support has separate
> controls for how tag check fail is reported. Including
>
>> +- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
>
> That may be less than optimal once userland starts uses tags itself, e.g.
> running qemu itself with an mte-aware malloc.
>
> Independent of that, there's also the TCO bit, which can be toggled by any
> piece of code that wants to disable checking locally.
Yes, I would expect the TCO bit is the best option for wrapping accesses
to make them unchecked.
> However, none of that is required for accessing tags. User space can always
> load/store tags via LDG/STG. That's going to be slow, though.
Yes as things stand LDG/STG is the way for user space to access tags.
Since I don't have any real hardware I can't really comment on speed.
> It's a shame that LDGM/STGM are privileged instructions. I don't understand
> why that was done, since there's absolutely nothing that those insns can do
> that you can't do with (up to) 16x LDG/STG.
It is a shame, however I suspect this is because to use those
instructions you need to know the block size held in GMID_EL1. And at
least in theory that could vary between CPUs.
> I think it might be worth adding some sort of kernel entry point that can bulk
> copy tags, e.g. page aligned quantities. But that's just a speed of migration
> thing and could come later.
When we have some real hardware it would be worth profiling this. At the
moment I've no idea whether the kernel entry overhead would make such an
interface useful from a performance perspective or not.
Steve
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Steven Price <steven.price@arm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Peter Maydell <Peter.Maydell@arm.com>,
Haibo Xu <Haibo.Xu@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
qemu-devel@nongnu.org, Juan Quintela <quintela@redhat.com>,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 0/2] MTE support for KVM guest
Date: Thu, 10 Sep 2020 11:24:51 +0100 [thread overview]
Message-ID: <842807ac-562a-36ce-8061-aa323341b605@arm.com> (raw)
In-Reply-To: <8e661984-70bc-790c-8636-39dcd8b00131@linaro.org>
On 10/09/2020 01:33, Richard Henderson wrote:
> On 9/4/20 9:00 AM, Steven Price wrote:
>> 3. Doesn't provide any new methods for the VMM to access the tags on
>> memory.
> ...
>> (3) may be problematic and I'd welcome input from those familiar with
>> VMMs. User space cannot access tags unless the memory is mapped with the
>> PROT_MTE flag. However enabling PROT_MTE will also enable tag checking
>> for the user space process (assuming the VMM enables tag checking for
>> the process)...
>
> The latest version of the kernel patches for user mte support has separate
> controls for how tag check fail is reported. Including
>
>> +- ``PR_MTE_TCF_NONE`` - *Ignore* tag check faults
>
> That may be less than optimal once userland starts uses tags itself, e.g.
> running qemu itself with an mte-aware malloc.
>
> Independent of that, there's also the TCO bit, which can be toggled by any
> piece of code that wants to disable checking locally.
Yes, I would expect the TCO bit is the best option for wrapping accesses
to make them unchecked.
> However, none of that is required for accessing tags. User space can always
> load/store tags via LDG/STG. That's going to be slow, though.
Yes as things stand LDG/STG is the way for user space to access tags.
Since I don't have any real hardware I can't really comment on speed.
> It's a shame that LDGM/STGM are privileged instructions. I don't understand
> why that was done, since there's absolutely nothing that those insns can do
> that you can't do with (up to) 16x LDG/STG.
It is a shame, however I suspect this is because to use those
instructions you need to know the block size held in GMID_EL1. And at
least in theory that could vary between CPUs.
> I think it might be worth adding some sort of kernel entry point that can bulk
> copy tags, e.g. page aligned quantities. But that's just a speed of migration
> thing and could come later.
When we have some real hardware it would be worth profiling this. At the
moment I've no idea whether the kernel entry overhead would make such an
interface useful from a performance perspective or not.
Steve
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-10 10:25 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-04 16:00 [PATCH v2 0/2] MTE support for KVM guest Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` [PATCH v2 1/2] arm64: kvm: Save/restore MTE registers Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` [PATCH v2 2/2] arm64: kvm: Introduce MTE VCPU feature Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-04 16:00 ` Steven Price
2020-09-09 15:48 ` Andrew Jones
2020-09-09 15:48 ` Andrew Jones
2020-09-09 15:48 ` Andrew Jones
2020-09-09 15:48 ` Andrew Jones
2020-09-09 15:53 ` Peter Maydell
2020-09-09 15:53 ` Peter Maydell
2020-09-09 15:53 ` Peter Maydell
2020-09-09 15:53 ` Peter Maydell
2020-09-10 6:38 ` Andrew Jones
2020-09-10 6:38 ` Andrew Jones
2020-09-10 6:38 ` Andrew Jones
2020-09-10 6:38 ` Andrew Jones
2020-09-10 10:01 ` Andrew Jones
2020-09-10 10:01 ` Andrew Jones
2020-09-10 10:01 ` Andrew Jones
2020-09-10 10:01 ` Andrew Jones
2020-09-10 9:21 ` Steven Price
2020-09-10 9:21 ` Steven Price
2020-09-10 9:21 ` Steven Price
2020-09-10 9:21 ` Steven Price
2020-09-10 11:49 ` Andrew Jones
2020-09-10 11:49 ` Andrew Jones
2020-09-10 11:49 ` Andrew Jones
2020-09-10 11:49 ` Andrew Jones
2020-09-07 15:28 ` [PATCH v2 0/2] MTE support for KVM guest Dr. David Alan Gilbert
2020-09-07 15:28 ` Dr. David Alan Gilbert
2020-09-07 15:28 ` Dr. David Alan Gilbert
2020-09-07 15:28 ` Dr. David Alan Gilbert
2020-09-09 9:15 ` Steven Price
2020-09-09 9:15 ` Steven Price
2020-09-09 9:15 ` Steven Price
2020-09-09 9:15 ` Steven Price
2020-09-09 15:25 ` Andrew Jones
2020-09-09 15:25 ` Andrew Jones
2020-09-09 15:25 ` Andrew Jones
2020-09-09 15:25 ` Andrew Jones
2020-09-09 16:04 ` Steven Price
2020-09-09 16:04 ` Steven Price
2020-09-09 16:04 ` Steven Price
2020-09-09 16:04 ` Steven Price
2020-09-10 6:29 ` Andrew Jones
2020-09-10 6:29 ` Andrew Jones
2020-09-10 6:29 ` Andrew Jones
2020-09-10 6:29 ` Andrew Jones
2020-09-10 9:21 ` Steven Price
2020-09-10 9:21 ` Steven Price
2020-09-10 9:21 ` Steven Price
2020-09-10 9:21 ` Steven Price
2020-09-10 13:56 ` Andrew Jones
2020-09-10 13:56 ` Andrew Jones
2020-09-10 13:56 ` Andrew Jones
2020-09-10 13:56 ` Andrew Jones
2020-09-10 14:14 ` Steven Price
2020-09-10 14:14 ` Steven Price
2020-09-10 14:14 ` Steven Price
2020-09-10 14:14 ` Steven Price
2020-09-10 1:45 ` Richard Henderson
2020-09-10 1:45 ` Richard Henderson
2020-09-10 1:45 ` Richard Henderson
2020-09-10 1:45 ` Richard Henderson
2020-09-10 5:44 ` Andrew Jones
2020-09-10 5:44 ` Andrew Jones
2020-09-10 5:44 ` Andrew Jones
2020-09-10 5:44 ` Andrew Jones
2020-09-10 13:27 ` Dr. David Alan Gilbert
2020-09-10 13:27 ` Dr. David Alan Gilbert
2020-09-10 13:27 ` Dr. David Alan Gilbert
2020-09-10 13:27 ` Dr. David Alan Gilbert
2020-09-10 13:39 ` Andrew Jones
2020-09-10 13:39 ` Andrew Jones
2020-09-10 13:39 ` Andrew Jones
2020-09-10 13:39 ` Andrew Jones
2020-09-10 0:33 ` Richard Henderson
2020-09-10 0:33 ` Richard Henderson
2020-09-10 0:33 ` Richard Henderson
2020-09-10 0:33 ` Richard Henderson
2020-09-10 10:24 ` Steven Price [this message]
2020-09-10 10:24 ` Steven Price
2020-09-10 10:24 ` Steven Price
2020-09-10 10:24 ` Steven Price
2020-09-10 15:36 ` Richard Henderson
2020-09-10 15:36 ` Richard Henderson
2020-09-10 15:36 ` Richard Henderson
2020-09-10 15:36 ` Richard Henderson
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