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From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, dri-devel@lists.freedesktop.org
Subject: [PATCH 11/19] drm/i915/display: add I915 conditional build to intel_dpio_phy.h
Date: Tue, 12 Sep 2023 14:06:38 +0300	[thread overview]
Message-ID: <978bc7263e8de10ffc1ef16086341dd629347c8e.1694514689.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1694514689.git.jani.nikula@intel.com>

Add stubs for !I915.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.h | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 9c7725dacb47..4d43dbbdf81c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -26,6 +26,7 @@ enum dpio_phy {
 	DPIO_PHY2,
 };
 
+#ifdef I915
 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
 			     enum dpio_phy *phy, enum dpio_channel *ch);
 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
@@ -70,5 +71,100 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state);
 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *old_crtc_state);
+#else
+static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+					   enum dpio_phy *phy, enum dpio_channel *ch)
+{
+}
+static inline void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
+						 const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+}
+static inline void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+}
+static inline bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
+					  enum dpio_phy phy)
+{
+	return false;
+}
+static inline bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
+					    enum dpio_phy phy)
+{
+	return true;
+}
+static inline u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
+{
+	return 0;
+}
+static inline void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+						   u8 lane_lat_optim_mask)
+{
+}
+static inline u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
+{
+	return 0;
+}
+static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
+{
+	return DPIO_CH0;
+}
+static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
+{
+	return DPIO_PHY0;
+}
+static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
+{
+	return DPIO_CH0;
+}
+static inline void chv_set_phy_signal_level(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *crtc_state,
+					    u32 deemph_reg_value, u32 margin_reg_value,
+					    bool uniq_trans_scale)
+{
+}
+static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *crtc_state,
+					    bool reset)
+{
+}
+static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+					      const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder)
+{
+}
+static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *old_crtc_state)
+{
+}
+
+static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *crtc_state,
+					    u32 demph_reg_value, u32 preemph_reg_value,
+					    u32 uniqtranscale_reg_value, u32 tx3_demph)
+{
+}
+static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+					      const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *old_crtc_state)
+{
+}
+#endif
 
 #endif /* __INTEL_DPIO_PHY_H__ */
-- 
2.39.2


WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 11/19] drm/i915/display: add I915 conditional build to intel_dpio_phy.h
Date: Tue, 12 Sep 2023 14:06:38 +0300	[thread overview]
Message-ID: <978bc7263e8de10ffc1ef16086341dd629347c8e.1694514689.git.jani.nikula@intel.com> (raw)
In-Reply-To: <cover.1694514689.git.jani.nikula@intel.com>

Add stubs for !I915.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.h | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 9c7725dacb47..4d43dbbdf81c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -26,6 +26,7 @@ enum dpio_phy {
 	DPIO_PHY2,
 };
 
+#ifdef I915
 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
 			     enum dpio_phy *phy, enum dpio_channel *ch);
 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
@@ -70,5 +71,100 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state);
 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *old_crtc_state);
+#else
+static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+					   enum dpio_phy *phy, enum dpio_channel *ch)
+{
+}
+static inline void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
+						 const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+}
+static inline void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+}
+static inline bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
+					  enum dpio_phy phy)
+{
+	return false;
+}
+static inline bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
+					    enum dpio_phy phy)
+{
+	return true;
+}
+static inline u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
+{
+	return 0;
+}
+static inline void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+						   u8 lane_lat_optim_mask)
+{
+}
+static inline u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
+{
+	return 0;
+}
+static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
+{
+	return DPIO_CH0;
+}
+static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
+{
+	return DPIO_PHY0;
+}
+static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
+{
+	return DPIO_CH0;
+}
+static inline void chv_set_phy_signal_level(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *crtc_state,
+					    u32 deemph_reg_value, u32 margin_reg_value,
+					    bool uniq_trans_scale)
+{
+}
+static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *crtc_state,
+					    bool reset)
+{
+}
+static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+					      const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder)
+{
+}
+static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *old_crtc_state)
+{
+}
+
+static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+					    const struct intel_crtc_state *crtc_state,
+					    u32 demph_reg_value, u32 preemph_reg_value,
+					    u32 uniqtranscale_reg_value, u32 tx3_demph)
+{
+}
+static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+					      const struct intel_crtc_state *crtc_state)
+{
+}
+static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *old_crtc_state)
+{
+}
+#endif
 
 #endif /* __INTEL_DPIO_PHY_H__ */
-- 
2.39.2


  parent reply	other threads:[~2023-09-12 11:08 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-12 11:06 [PATCH 00/19] drm/i915: prepare for xe driver display integration Jani Nikula
2023-09-12 11:06 ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 01/19] drm/i915: define I915 during i915 driver build Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 02/19] drm/i915/display: add I915 conditional build to intel_lvds.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 03/19] drm/i915/display: add I915 conditional build to hsw_ips.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [Intel-gfx] [PATCH 04/19] drm/i915/display: add I915 conditional build to i9xx_plane.h Jani Nikula
2023-09-12 11:06   ` Jani Nikula
2023-09-12 11:06 ` [Intel-gfx] [PATCH 05/19] drm/i915/display: add I915 conditional build to intel_lpe_audio.h Jani Nikula
2023-09-12 11:06   ` Jani Nikula
2023-09-12 11:06 ` [PATCH 06/19] drm/i915/display: add I915 conditional build to intel_pch_refclk.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 07/19] drm/i915/display: add I915 conditional build to intel_pch_display.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 08/19] drm/i915/display: add I915 conditional build to intel_sprite.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [Intel-gfx] [PATCH 09/19] drm/i915/display: add I915 conditional build to intel_overlay.h Jani Nikula
2023-09-12 11:06   ` Jani Nikula
2023-09-12 11:06 ` [PATCH 10/19] drm/i915/display: add I915 conditional build to g4x_dp.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` Jani Nikula [this message]
2023-09-12 11:06   ` [Intel-gfx] [PATCH 11/19] drm/i915/display: add I915 conditional build to intel_dpio_phy.h Jani Nikula
2023-09-12 11:06 ` [PATCH 12/19] drm/i915/display: add I915 conditional build to intel_crt.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 13/19] drm/i915/display: add I915 conditional build to vlv_dsi.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 14/19] drm/i915/display: add I915 conditional build to i9xx_wm.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 15/19] drm/i915/display: add I915 conditional build to g4x_hdmi.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 16/19] drm/i915/display: add I915 conditional build to intel_dvo.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [PATCH 17/19] drm/i915/display: add I915 conditional build to intel_sdvo.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 11:06 ` [Intel-gfx] [PATCH 18/19] drm/i915/display: add I915 conditional build to intel_tv.h Jani Nikula
2023-09-12 11:06   ` Jani Nikula
2023-09-12 11:06 ` [PATCH 19/19] drm/i915/display: add I915 conditional build to vlv_dsi_pll.h Jani Nikula
2023-09-12 11:06   ` [Intel-gfx] " Jani Nikula
2023-09-12 19:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: prepare for xe driver display integration Patchwork
2023-09-12 19:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-12 19:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-09-13 20:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: prepare for xe driver display integration (rev2) Patchwork
2023-09-13 20:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-13 20:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-09-14  0:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-14 14:53 ` [PATCH 00/19] drm/i915: prepare for xe driver display integration Rodrigo Vivi
2023-09-14 14:53   ` [Intel-gfx] " Rodrigo Vivi
2023-09-29 11:03   ` Jani Nikula
2023-09-29 11:03     ` [Intel-gfx] " Jani Nikula

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