From: "Yang, Fei" <fei.yang@intel.com> To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>, "Roper, Matthew D" <matthew.d.roper@intel.com>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org> Subject: RE: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level Date: Sun, 23 Apr 2023 06:12:41 +0000 [thread overview] Message-ID: <BYAPR11MB25676CAFE8FA0CD0E6ED6EA69A669@BYAPR11MB2567.namprd11.prod.outlook.com> (raw) In-Reply-To: <705b5e5b-78cd-857f-ad26-80835217520c@linux.intel.com> > On 20/04/2023 00:00, fei.yang@intel.com wrote: >> From: Fei Yang <fei.yang@intel.com> >> >> Currently the KMD is using enum i915_cache_level to set caching policy >> for buffer objects. This is flaky because the PAT index which really >> controls the caching behavior in PTE has far more levels than what's >> defined in the enum. In addition, the PAT index is platform dependent, >> having to translate between i915_cache_level and PAT index is not >> reliable, and makes the code more complicated. >> >> From UMD's perspective there is also a necessity to set caching policy for >> performance fine tuning. It's much easier for the UMD to directly use >> PAT index because the behavior of each PAT index is clearly defined in Bspec. >> Having the abstracted i915_cache_level sitting in between would only >> cause more ambiguity. >> >> For these reasons this patch replaces i915_cache_level with PAT index. >> Also note, the cache_level is not completely removed yet, because the >> KMD still has the need of creating buffer objects with simple cache >> settings such as cached, uncached, or writethrough. For such simple >> cases, using cache_level would help simplify the code. >> >> Cc: Chris Wilson <chris.p.wilson@linux.intel.com> >> Cc: Matt Roper <matthew.d.roper@intel.com> >> Signed-off-by: Fei Yang <fei.yang@intel.com> >> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> > > [snip] > >> >> bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object >> *obj) @@ -267,7 +267,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, >> { >> int ret; >> >> - if (obj->cache_level == cache_level) >> + if (i915_gem_object_has_cache_level(obj, cache_level)) >> return 0; > > When userspace calls i915_gem_set_caching_ioctl We are ending the support for set_caching_ioctl. > after having set the PAT index explicitly this will make it silently succeed > regardless of the cache level passed in, no? Because of: Yes, that's the point. For objects created by userspace with PAT index set, KMD is not supposed to touch the setting. > +bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj, > + enum i915_cache_level lvl) > +{ > + /* > + * cache_level == I915_CACHE_INVAL indicates the UMD's have set the > + * caching policy through pat_index, in which case the KMD should > + * leave the coherency to be managed by user space, simply return > + * true here. > + */ > + if (obj->cache_level == I915_CACHE_INVAL) > + return true; > > I think we need to let it know it is doing it wrong with an error. This is not an error, by design userspace should know exactly what it's doing. -Fei > Regards, > > Tvrtko
WARNING: multiple messages have this Message-ID (diff)
From: "Yang, Fei" <fei.yang@intel.com> To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>, "Roper, Matthew D" <matthew.d.roper@intel.com>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level Date: Sun, 23 Apr 2023 06:12:41 +0000 [thread overview] Message-ID: <BYAPR11MB25676CAFE8FA0CD0E6ED6EA69A669@BYAPR11MB2567.namprd11.prod.outlook.com> (raw) In-Reply-To: <705b5e5b-78cd-857f-ad26-80835217520c@linux.intel.com> > On 20/04/2023 00:00, fei.yang@intel.com wrote: >> From: Fei Yang <fei.yang@intel.com> >> >> Currently the KMD is using enum i915_cache_level to set caching policy >> for buffer objects. This is flaky because the PAT index which really >> controls the caching behavior in PTE has far more levels than what's >> defined in the enum. In addition, the PAT index is platform dependent, >> having to translate between i915_cache_level and PAT index is not >> reliable, and makes the code more complicated. >> >> From UMD's perspective there is also a necessity to set caching policy for >> performance fine tuning. It's much easier for the UMD to directly use >> PAT index because the behavior of each PAT index is clearly defined in Bspec. >> Having the abstracted i915_cache_level sitting in between would only >> cause more ambiguity. >> >> For these reasons this patch replaces i915_cache_level with PAT index. >> Also note, the cache_level is not completely removed yet, because the >> KMD still has the need of creating buffer objects with simple cache >> settings such as cached, uncached, or writethrough. For such simple >> cases, using cache_level would help simplify the code. >> >> Cc: Chris Wilson <chris.p.wilson@linux.intel.com> >> Cc: Matt Roper <matthew.d.roper@intel.com> >> Signed-off-by: Fei Yang <fei.yang@intel.com> >> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> > > [snip] > >> >> bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object >> *obj) @@ -267,7 +267,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, >> { >> int ret; >> >> - if (obj->cache_level == cache_level) >> + if (i915_gem_object_has_cache_level(obj, cache_level)) >> return 0; > > When userspace calls i915_gem_set_caching_ioctl We are ending the support for set_caching_ioctl. > after having set the PAT index explicitly this will make it silently succeed > regardless of the cache level passed in, no? Because of: Yes, that's the point. For objects created by userspace with PAT index set, KMD is not supposed to touch the setting. > +bool i915_gem_object_has_cache_level(const struct drm_i915_gem_object *obj, > + enum i915_cache_level lvl) > +{ > + /* > + * cache_level == I915_CACHE_INVAL indicates the UMD's have set the > + * caching policy through pat_index, in which case the KMD should > + * leave the coherency to be managed by user space, simply return > + * true here. > + */ > + if (obj->cache_level == I915_CACHE_INVAL) > + return true; > > I think we need to let it know it is doing it wrong with an error. This is not an error, by design userspace should know exactly what it's doing. -Fei > Regards, > > Tvrtko
next prev parent reply other threads:[~2023-04-23 6:12 UTC|newest] Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-19 23:00 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-19 23:00 ` [PATCH 1/8] drm/i915/mtl: Set has_llc=0 fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 10:20 ` Das, Nirmoy 2023-04-20 10:20 ` Das, Nirmoy 2023-04-19 23:00 ` [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 20:29 ` Matt Roper 2023-04-19 23:00 ` [PATCH 3/8] drm/i915/mtl: Add PTE encode function fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 20:40 ` Matt Roper 2023-04-21 17:27 ` Yang, Fei 2023-04-21 17:42 ` Matt Roper 2023-04-23 7:37 ` Yang, Fei 2023-04-23 7:37 ` Yang, Fei 2023-04-24 17:20 ` Matt Roper 2023-04-24 18:41 ` Yang, Fei 2023-04-19 23:00 ` [PATCH 4/8] drm/i915/mtl: workaround coherency issue for Media fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 8:26 ` Andrzej Hajda 2023-04-20 11:36 ` Das, Nirmoy 2023-04-20 11:36 ` Das, Nirmoy 2023-04-20 20:52 ` Matt Roper 2023-04-19 23:00 ` [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 21:05 ` Matt Roper 2023-04-19 23:00 ` [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 8:45 ` Andrzej Hajda 2023-04-20 21:14 ` Matt Roper 2023-04-19 23:00 ` [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 10:13 ` Andrzej Hajda 2023-04-20 12:39 ` Tvrtko Ursulin 2023-04-20 20:34 ` Yang, Fei 2023-04-21 8:43 ` Tvrtko Ursulin 2023-04-21 10:17 ` Tvrtko Ursulin 2023-04-23 6:12 ` Yang, Fei [this message] 2023-04-23 6:12 ` Yang, Fei 2023-04-24 8:41 ` Tvrtko Ursulin 2023-04-21 11:39 ` Tvrtko Ursulin 2023-04-23 6:52 ` Yang, Fei 2023-04-23 6:52 ` Yang, Fei 2023-04-24 9:22 ` Tvrtko Ursulin 2023-04-19 23:00 ` [PATCH 8/8] drm/i915: Allow user to set cache at BO creation fei.yang 2023-04-19 23:00 ` [Intel-gfx] " fei.yang 2023-04-20 11:39 ` Andi Shyti 2023-04-20 11:39 ` [Intel-gfx] " Andi Shyti 2023-04-20 13:06 ` Tvrtko Ursulin 2023-04-20 16:11 ` Yang, Fei 2023-04-20 16:29 ` Andi Shyti 2023-04-20 16:29 ` Andi Shyti 2023-04-21 20:48 ` Jordan Justen 2023-04-21 20:48 ` Jordan Justen [not found] ` <BYAPR11MB2567F03AD43D7E2DE2628D5D9A669@BYAPR11MB2567.namprd11.prod.outlook.com> [not found] ` <168232538771.392286.3227368099155268955@jljusten-skl> 2023-04-24 9:08 ` Tvrtko Ursulin 2023-04-24 9:08 ` Tvrtko Ursulin 2023-04-24 17:13 ` Jordan Justen 2023-04-24 17:13 ` Jordan Justen 2023-04-25 13:41 ` IOCTL feature detection (Was: Re: [Intel-gfx] [PATCH 8/8] drm/i915: Allow user to set cache at BO creation) Joonas Lahtinen 2023-04-25 13:41 ` [Intel-gfx] IOCTL feature detection (Was: " Joonas Lahtinen 2023-04-25 17:21 ` IOCTL feature detection (Was: Re: [Intel-gfx] " Teres Alexis, Alan Previn 2023-04-25 17:21 ` [Intel-gfx] IOCTL feature detection (Was: " Teres Alexis, Alan Previn 2023-04-25 18:19 ` IOCTL feature detection (Was: Re: [Intel-gfx] " Jordan Justen 2023-04-25 18:19 ` [Intel-gfx] IOCTL feature detection (Was: " Jordan Justen 2023-04-26 11:52 ` IOCTL feature detection (Was: Re: [Intel-gfx] " Daniel Vetter 2023-04-26 11:52 ` [Intel-gfx] IOCTL feature detection (Was: " Daniel Vetter 2023-04-26 16:48 ` IOCTL feature detection (Was: Re: [Intel-gfx] " Teres Alexis, Alan Previn 2023-04-26 16:48 ` [Intel-gfx] IOCTL feature detection (Was: " Teres Alexis, Alan Previn 2023-04-26 18:10 ` IOCTL feature detection (Was: Re: [Intel-gfx] " Ceraolo Spurio, Daniele 2023-04-26 18:10 ` [Intel-gfx] IOCTL feature detection (Was: " Ceraolo Spurio, Daniele 2023-04-26 20:04 ` IOCTL feature detection (Was: Re: [Intel-gfx] " Jordan Justen 2023-04-26 20:04 ` [Intel-gfx] IOCTL feature detection (Was: " Jordan Justen 2023-04-19 23:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev8) Patchwork 2023-04-19 23:51 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2023-04-20 11:30 ` [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL Andi Shyti -- strict thread matches above, loose matches on Subject: below -- 2023-04-19 21:12 fei.yang 2023-04-19 21:12 ` [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang 2023-04-19 22:09 ` Andi Shyti 2023-04-19 18:09 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-19 18:09 ` [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang 2023-04-17 6:24 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-17 6:25 ` [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang 2023-04-19 12:16 ` Andi Shyti
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