From: Andrew Pinski <pinskia@gmail.com> To: Vineet Gupta <vineetg@rivosinc.com> Cc: "Richard Henderson" <richard.henderson@linaro.org>, "Florian Weimer" <fweimer@redhat.com>, "Björn Töpel" <bjorn@kernel.org>, "Darius Rad" <darius@bluespec.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Andrew Waterman" <andrew@sifive.com>, stillson@rivosinc.com, "Paul Walmsley" <paul.walmsley@sifive.com>, anup@brainfault.org, atishp@atishpatra.org, guoren@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>, greentime.hu@sifive.com, vincent.chen@sifive.com, andy.chiu@sifive.com, arnd@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, libc-alpha@sourceware.org, christoph.muellner@vrull.eu, "Aaron Durbin" <adurbin@rivosinc.com>, linux@rivosinc.com Subject: Re: RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Date: Thu, 15 Dec 2022 10:59:47 -0800 [thread overview] Message-ID: <CA+=Sn1nH-b8OigfFBNKT_ECr5DL-jJ5XU+H9pA9g5gF=8YQNMQ@mail.gmail.com> (raw) In-Reply-To: <15d902d0-4492-f828-7147-164319d741f9@rivosinc.com> On Thu, Dec 15, 2022 at 10:57 AM Vineet Gupta <vineetg@rivosinc.com> wrote: > > > > On 12/15/22 07:33, Richard Henderson wrote: > > On 12/15/22 04:28, Florian Weimer via Libc-alpha wrote: > >> * Björn Töpel: > >> > >>>> For SVE, it is in fact disabled by default in the kernel. When a > >>>> thread > >>>> executes the first SVE instruction, it will cause an exception, the > >>>> kernel > >>>> will allocate memory for SVE state and enable TIF_SVE. Further use > >>>> of SVE > >>>> instructions will proceed without exceptions. Although SVE is > >>>> disabled by > >>>> default, it is enabled automatically. Since this is done > >>>> automatically > >>>> during an exception handler, there is no opportunity for memory > >>>> allocation > >>>> errors to be reported, as there are in the AMX case. > >>> > >>> Glibc has an SVE optimized memcpy, right? Doesn't that mean that pretty > >>> much all processes on an SVE capable system will enable SVE > >>> (lazily)? If > >>> so, that's close to "enabled by default" (unless SVE is disabled system > >>> wide). > >> > >> Yes, see sysdeps/aarch64/multiarch/memcpy.c: > >> > >> static inline __typeof (__redirect_memcpy) * > >> select_memcpy_ifunc (void) > >> { > >> INIT_ARCH (); > >> if (sve && HAVE_AARCH64_SVE_ASM) > >> { > >> if (IS_A64FX (midr)) > >> return __memcpy_a64fx; > >> return __memcpy_sve; > >> } > >> if (IS_THUNDERX (midr)) > >> return __memcpy_thunderx; > >> if (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr)) > >> return __memcpy_thunderx2; > >> if (IS_FALKOR (midr) || IS_PHECDA (midr)) > >> return __memcpy_falkor; > >> return __memcpy_generic; > >> } > >> And the __memcpy_sve implementation actually uses SVE. > >> > >> If there were a prctl to select the vector width and enable the vector > >> extension, we'd have to pick a width in glibc anyway. > > > > There *is* a prctl to adjust the SVE vector width, but glibc does not > > need to select because SVE dynamically adjusts to the currently > > enabled width. The kernel selects a default width that fits within > > the default signal frame size. > > > > The other thing of note for SVE is that, with the default function ABI > > all of the SVE state is call-clobbered, which allows the kernel to > > drop instead of save state across system calls. (There is a separate > > vector function call ABI when SVE types are used.) > > For the RV psABI, it is similar - all V regs are > caller-saved/call-clobbered [1] and syscalls are not required to > preserve V regs [2] > However last I checked ARM documentation the ABI doc seemed to suggest > that some (parts) of the SVE regs are callee-saved [3] Yes the lower 64 bits which overlap with the floating point registers. Thanks, Andrew Pinski > > > > > So while strcpy may enable SVE for the thread, the next syscall may > > disable it again. > > Next syscall could trash them, but will it disable SVE ? Despite > syscall/function-call clobbers, using V in tight loops such as mem*/str* > still is a win. > > > [1] > https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc > [2] > https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc > [3] > https://github.com/ARM-software/abi-aa/blob/2982a9f3b512a5bfdc9e3fea5d3b298f9165c36b/aapcs64/aapcs64.rst#the-base-procedure-call-standard > Sec 6.1.3 ".... In other cases it need only preserve the low 64 bits of > z8-z15" >
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Pinski <pinskia@gmail.com> To: Vineet Gupta <vineetg@rivosinc.com> Cc: "Richard Henderson" <richard.henderson@linaro.org>, "Florian Weimer" <fweimer@redhat.com>, "Björn Töpel" <bjorn@kernel.org>, "Darius Rad" <darius@bluespec.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Andrew Waterman" <andrew@sifive.com>, stillson@rivosinc.com, "Paul Walmsley" <paul.walmsley@sifive.com>, anup@brainfault.org, atishp@atishpatra.org, guoren@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>, greentime.hu@sifive.com, vincent.chen@sifive.com, andy.chiu@sifive.com, arnd@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, libc-alpha@sourceware.org, christoph.muellner@vrull.eu, "Aaron Durbin" <adurbin@rivosinc.com>, linux@rivosinc.com Subject: Re: RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Date: Thu, 15 Dec 2022 10:59:47 -0800 [thread overview] Message-ID: <CA+=Sn1nH-b8OigfFBNKT_ECr5DL-jJ5XU+H9pA9g5gF=8YQNMQ@mail.gmail.com> (raw) In-Reply-To: <15d902d0-4492-f828-7147-164319d741f9@rivosinc.com> On Thu, Dec 15, 2022 at 10:57 AM Vineet Gupta <vineetg@rivosinc.com> wrote: > > > > On 12/15/22 07:33, Richard Henderson wrote: > > On 12/15/22 04:28, Florian Weimer via Libc-alpha wrote: > >> * Björn Töpel: > >> > >>>> For SVE, it is in fact disabled by default in the kernel. When a > >>>> thread > >>>> executes the first SVE instruction, it will cause an exception, the > >>>> kernel > >>>> will allocate memory for SVE state and enable TIF_SVE. Further use > >>>> of SVE > >>>> instructions will proceed without exceptions. Although SVE is > >>>> disabled by > >>>> default, it is enabled automatically. Since this is done > >>>> automatically > >>>> during an exception handler, there is no opportunity for memory > >>>> allocation > >>>> errors to be reported, as there are in the AMX case. > >>> > >>> Glibc has an SVE optimized memcpy, right? Doesn't that mean that pretty > >>> much all processes on an SVE capable system will enable SVE > >>> (lazily)? If > >>> so, that's close to "enabled by default" (unless SVE is disabled system > >>> wide). > >> > >> Yes, see sysdeps/aarch64/multiarch/memcpy.c: > >> > >> static inline __typeof (__redirect_memcpy) * > >> select_memcpy_ifunc (void) > >> { > >> INIT_ARCH (); > >> if (sve && HAVE_AARCH64_SVE_ASM) > >> { > >> if (IS_A64FX (midr)) > >> return __memcpy_a64fx; > >> return __memcpy_sve; > >> } > >> if (IS_THUNDERX (midr)) > >> return __memcpy_thunderx; > >> if (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr)) > >> return __memcpy_thunderx2; > >> if (IS_FALKOR (midr) || IS_PHECDA (midr)) > >> return __memcpy_falkor; > >> return __memcpy_generic; > >> } > >> And the __memcpy_sve implementation actually uses SVE. > >> > >> If there were a prctl to select the vector width and enable the vector > >> extension, we'd have to pick a width in glibc anyway. > > > > There *is* a prctl to adjust the SVE vector width, but glibc does not > > need to select because SVE dynamically adjusts to the currently > > enabled width. The kernel selects a default width that fits within > > the default signal frame size. > > > > The other thing of note for SVE is that, with the default function ABI > > all of the SVE state is call-clobbered, which allows the kernel to > > drop instead of save state across system calls. (There is a separate > > vector function call ABI when SVE types are used.) > > For the RV psABI, it is similar - all V regs are > caller-saved/call-clobbered [1] and syscalls are not required to > preserve V regs [2] > However last I checked ARM documentation the ABI doc seemed to suggest > that some (parts) of the SVE regs are callee-saved [3] Yes the lower 64 bits which overlap with the floating point registers. Thanks, Andrew Pinski > > > > > So while strcpy may enable SVE for the thread, the next syscall may > > disable it again. > > Next syscall could trash them, but will it disable SVE ? Despite > syscall/function-call clobbers, using V in tight loops such as mem*/str* > still is a win. > > > [1] > https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc > [2] > https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc > [3] > https://github.com/ARM-software/abi-aa/blob/2982a9f3b512a5bfdc9e3fea5d3b298f9165c36b/aapcs64/aapcs64.rst#the-base-procedure-call-standard > Sec 6.1.3 ".... In other cases it need only preserve the low 64 bits of > z8-z15" > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-15 19:00 UTC|newest] Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-21 21:43 [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson [not found] ` <4b6e20fb-d013-0a09-0b74-b6c46e045af3@rivosinc.com> [not found] ` <CAJF2gTSPoKu_owEb6+MLhAgK5nz2FTRDkTn4qfXF4KyA-XTwvw@mail.gmail.com> [not found] ` <CAJF2gTT_z96V3kjPtr9hpTq8XRn0x=91wFNPYFFdetAA2u-01Q@mail.gmail.com> 2022-11-04 9:13 ` Conor.Dooley 2022-11-04 18:04 ` Vineet Gupta 2022-09-21 21:43 ` [PATCH v12 03/17] riscv: Add new csr defines related to vector extension Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2023-01-23 11:24 ` Heiko Stübner 2023-01-23 11:24 ` Heiko Stübner 2022-09-21 21:43 ` [PATCH v12 04/17] riscv: Add vector feature to compile Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-11-07 17:21 ` Björn Töpel 2022-11-07 17:21 ` Björn Töpel 2022-11-08 0:04 ` Vineet Gupta 2022-11-08 0:04 ` Vineet Gupta 2022-11-08 7:56 ` Conor Dooley 2022-11-08 7:56 ` Conor Dooley 2022-11-08 17:17 ` Vineet Gupta 2022-11-08 17:17 ` Vineet Gupta 2022-11-08 17:22 ` Conor Dooley 2022-11-08 17:22 ` Conor Dooley 2022-11-13 16:16 ` Conor.Dooley 2022-11-13 16:16 ` Conor.Dooley 2022-11-15 17:38 ` Vineet Gupta 2022-11-15 17:38 ` Vineet Gupta 2022-11-15 22:17 ` Conor Dooley 2022-11-15 22:17 ` Conor Dooley 2022-12-15 0:40 ` Atish Patra 2022-12-15 0:40 ` Atish Patra 2022-09-21 21:43 ` [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-22 4:23 ` Samuel Holland 2022-09-22 4:23 ` Samuel Holland 2022-09-23 16:27 ` Chris Stillson 2022-09-23 16:27 ` Chris Stillson 2022-09-24 18:01 ` Conor Dooley 2022-09-24 18:01 ` Conor Dooley 2022-11-04 4:10 ` Vineet Gupta 2022-11-04 4:10 ` Vineet Gupta 2022-11-04 4:33 ` Vineet Gupta 2022-11-04 4:33 ` Vineet Gupta 2022-09-21 21:43 ` [PATCH v12 06/17] riscv: Reset vector register Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-11-04 5:01 ` Vineet Gupta 2022-11-04 5:01 ` Vineet Gupta 2022-11-04 8:45 ` Guo Ren 2022-11-04 8:45 ` Guo Ren 2023-01-20 12:20 ` Heiko Stübner 2023-01-20 12:20 ` Heiko Stübner 2022-09-21 21:43 ` [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-11-04 5:13 ` Vineet Gupta 2022-11-04 5:13 ` Vineet Gupta 2022-09-21 21:43 ` [PATCH v12 08/17] riscv: Add task switch support for vector Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-11-04 22:08 ` Vineet Gupta 2022-11-04 22:08 ` Vineet Gupta 2022-09-21 21:43 ` [PATCH v12 09/17] riscv: Add ptrace vector support Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-11-08 1:38 ` Vineet Gupta 2022-11-08 1:38 ` Vineet Gupta 2022-11-14 20:01 ` Arnd Bergmann 2022-11-14 20:01 ` Arnd Bergmann 2022-09-21 21:43 ` [PATCH v12 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-11-09 1:27 ` Vineet Gupta 2022-11-09 1:27 ` Vineet Gupta 2022-09-21 21:43 ` [PATCH v12 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 12/17] riscv: Add support for kernel mode vector Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 13/17] riscv: Add vector extension XOR implementation Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` [PATCH v12 17/17] riscv: prctl to enable vector commands Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-09-21 21:43 ` Chris Stillson 2022-12-09 5:16 ` RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Vineet Gupta 2022-12-09 5:16 ` Vineet Gupta 2022-12-09 6:27 ` Palmer Dabbelt 2022-12-09 6:27 ` Palmer Dabbelt 2022-12-09 7:42 ` Andrew Waterman 2022-12-09 7:42 ` Andrew Waterman 2022-12-09 10:02 ` Florian Weimer 2022-12-09 10:02 ` Florian Weimer 2022-12-09 12:21 ` Darius Rad 2022-12-09 12:21 ` Darius Rad 2022-12-09 12:32 ` Florian Weimer 2022-12-09 12:32 ` Florian Weimer 2022-12-09 12:42 ` Darius Rad 2022-12-09 12:42 ` Darius Rad 2022-12-09 13:04 ` Florian Weimer 2022-12-09 13:04 ` Florian Weimer 2022-12-09 17:21 ` Palmer Dabbelt 2022-12-09 17:21 ` Palmer Dabbelt 2022-12-09 19:42 ` Vineet Gupta 2022-12-09 19:42 ` Vineet Gupta 2022-12-09 19:58 ` Andrew Waterman 2022-12-09 19:58 ` Andrew Waterman 2022-12-13 16:43 ` Darius Rad 2022-12-13 16:43 ` Darius Rad 2022-12-14 20:07 ` Vineet Gupta 2022-12-14 20:07 ` Vineet Gupta 2022-12-14 23:13 ` Samuel Holland 2022-12-14 23:13 ` Samuel Holland 2022-12-15 2:09 ` Darius Rad 2022-12-15 2:09 ` Darius Rad 2022-12-15 11:48 ` Björn Töpel 2022-12-15 11:48 ` Björn Töpel 2022-12-15 12:28 ` Florian Weimer 2022-12-15 12:28 ` Florian Weimer 2022-12-15 15:33 ` Richard Henderson 2022-12-15 15:33 ` Richard Henderson 2022-12-15 18:57 ` Vineet Gupta 2022-12-15 18:57 ` Vineet Gupta 2022-12-15 18:59 ` Andrew Pinski [this message] 2022-12-15 18:59 ` Andrew Pinski 2022-12-15 19:01 ` Andrew Pinski 2022-12-15 19:01 ` Andrew Pinski 2022-12-15 19:56 ` Richard Henderson 2022-12-15 19:56 ` Richard Henderson 2022-12-09 13:58 ` Icenowy Zheng 2022-12-09 13:58 ` Icenowy Zheng 2023-01-23 11:20 ` [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Heiko Stübner 2023-01-23 11:20 ` Heiko Stübner
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