Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller

From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	 linux-arm-kernel@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	 Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller
Date: Mon, 26 Feb 2024 16:00:53 +0000	[thread overview]
Message-ID: <CA+V-a8stTXWue+oCLpCooL5WxXJofovjtxkEcEk_SB0_RZdz0w@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdWwn2nVx=vebT+Egas+b_dt7d28eN_ykrA+ckZ2GPuXHQ@mail.gmail.com>

Hi Geert,

On Mon, Feb 26, 2024 at 3:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > > > +  clocks:
> > > > +    items:
> > > > +      - description: Clock from external oscillator
> > >
> > > Isn't this SYS_0_PCLK inside the CPG?
> > >
> > As per the block diagram (figure 4.4-3), if we follow the clock source
> > for SYS it traces back to 24MHz Oscillator. Let me know how you want
> > me to describe this please.
>
> Yes, that is the diagram I was looking at.
> MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK.
>
> MAIN OSC 24 MHz is a clock input to the CPG.
> MAINCLK is a CPG internal core clock.
> SYS_0_PCLK is a CPG clock output, serving as the SYS module clock.
>
Agreed.

> I think the standard "maxItems: 1" would be fine, and no description
> is needed.
>
OK, makes sense.

> > > > +
> > > > +  resets:
> > > > +    items:
> > > > +      - description: SYS_0_PRESETN reset signal
>
> Same here.
>
Ok.

Cheers,
Prabhakar