From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro <fabrizio.castro.jz@renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Date: Mon, 26 Feb 2024 14:00:20 +0000 [thread overview] Message-ID: <CA+V-a8uNaRL7wE0SmwmiCq3o798-2Kd-fegKJ2Tep5mZuS2O2w@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdV3eVTek9sYwXbqu98ta8wx197GMc-k3q1RZRb8ar=jFg@mail.gmail.com> Hi Geert, Thank you for the review. On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add DT binding documentation for System Controller (SYS) found on > > RZ/V2H{P} ("R9A09G057") SoC's. > > RZ/V2H(P) > > > > > SYS block contains the SYS_LSI_DEVID register which can be used to > > retrieve SoC version information. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml > > @@ -0,0 +1,59 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/V2H{P} System Controller (SYS) > > + > > +maintainers: > > + - Geert Uytterhoeven <geert+renesas@glider.be> > > + > > +description: > > + The RZ/V2H{P} SYS (System Controller) controls the overall > > RZ/V2H(P) > OK. > > + configuration of the LSI and supports the following functions, > > + - Trust zone control > > + - Extend access by specific masters to address beyond 4GB space > > + - GBETH configuration > > + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU > > + - LSI version > > + - WDT stop control > > + - General registers > > + > > +properties: > > + compatible: > > + const: renesas,r9a09g057-sys > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Clock from external oscillator > > Isn't this SYS_0_PCLK inside the CPG? > As per the block diagram (figure 4.4-3), if we follow the clock source for SYS it traces back to 24MHz Oscillator. Let me know how you want me to describe this please. > > + > > + resets: > > + items: > > + - description: SYS_0_PRESETN reset signal > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - resets > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + extal_clk: extal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + }; > > + > > + sys: system-controller@10430000 { > > + compatible = "renesas,r9a09g057-sys"; > > + reg = <0x10430000 0x10000>; > > + clocks = <&extal_clk>; > > clocks = <&cpg 1>; > > (I guess it will be 1 ;-) > Yep indeed ;) Cheers, Prabhakar > > + resets = <&cpg 1>; > > + }; > > Gr{oetje,eeting}s, > > Geert > > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
WARNING: multiple messages have this Message-ID (diff)
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro <fabrizio.castro.jz@renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Date: Mon, 26 Feb 2024 14:00:20 +0000 [thread overview] Message-ID: <CA+V-a8uNaRL7wE0SmwmiCq3o798-2Kd-fegKJ2Tep5mZuS2O2w@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdV3eVTek9sYwXbqu98ta8wx197GMc-k3q1RZRb8ar=jFg@mail.gmail.com> Hi Geert, Thank you for the review. On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add DT binding documentation for System Controller (SYS) found on > > RZ/V2H{P} ("R9A09G057") SoC's. > > RZ/V2H(P) > > > > > SYS block contains the SYS_LSI_DEVID register which can be used to > > retrieve SoC version information. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml > > @@ -0,0 +1,59 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/V2H{P} System Controller (SYS) > > + > > +maintainers: > > + - Geert Uytterhoeven <geert+renesas@glider.be> > > + > > +description: > > + The RZ/V2H{P} SYS (System Controller) controls the overall > > RZ/V2H(P) > OK. > > + configuration of the LSI and supports the following functions, > > + - Trust zone control > > + - Extend access by specific masters to address beyond 4GB space > > + - GBETH configuration > > + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU > > + - LSI version > > + - WDT stop control > > + - General registers > > + > > +properties: > > + compatible: > > + const: renesas,r9a09g057-sys > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Clock from external oscillator > > Isn't this SYS_0_PCLK inside the CPG? > As per the block diagram (figure 4.4-3), if we follow the clock source for SYS it traces back to 24MHz Oscillator. Let me know how you want me to describe this please. > > + > > + resets: > > + items: > > + - description: SYS_0_PRESETN reset signal > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - resets > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + extal_clk: extal-clk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + }; > > + > > + sys: system-controller@10430000 { > > + compatible = "renesas,r9a09g057-sys"; > > + reg = <0x10430000 0x10000>; > > + clocks = <&extal_clk>; > > clocks = <&cpg 1>; > > (I guess it will be 1 ;-) > Yep indeed ;) Cheers, Prabhakar > > + resets = <&cpg 1>; > > + }; > > Gr{oetje,eeting}s, > > Geert > > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-02-26 14:01 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-19 16:09 [PATCH 0/4] Add new Renesas RZ/V2H SoC Prabhakar 2024-02-19 16:09 ` Prabhakar 2024-02-19 16:09 ` [PATCH 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H{P} SoC variants Prabhakar 2024-02-19 16:09 ` Prabhakar 2024-02-20 9:50 ` Krzysztof Kozlowski 2024-02-20 9:50 ` Krzysztof Kozlowski 2024-02-26 13:41 ` Geert Uytterhoeven 2024-02-26 13:41 ` Geert Uytterhoeven 2024-02-26 13:55 ` Lad, Prabhakar 2024-02-26 13:55 ` Lad, Prabhakar 2024-02-19 16:09 ` [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller Prabhakar 2024-02-19 16:09 ` Prabhakar 2024-02-20 9:51 ` Krzysztof Kozlowski 2024-02-20 9:51 ` Krzysztof Kozlowski 2024-02-22 12:44 ` Lad, Prabhakar 2024-02-22 12:44 ` Lad, Prabhakar 2024-02-26 13:41 ` Geert Uytterhoeven 2024-02-26 13:41 ` Geert Uytterhoeven 2024-02-26 14:00 ` Lad, Prabhakar [this message] 2024-02-26 14:00 ` Lad, Prabhakar 2024-02-26 15:14 ` Geert Uytterhoeven 2024-02-26 15:14 ` Geert Uytterhoeven 2024-02-26 16:00 ` Lad, Prabhakar 2024-02-26 16:00 ` Lad, Prabhakar 2024-02-19 16:09 ` [PATCH 3/4] soc: renesas: Add identification support for RZ/V2H SoC Prabhakar 2024-02-19 16:09 ` Prabhakar 2024-02-26 13:42 ` Geert Uytterhoeven 2024-02-26 13:42 ` Geert Uytterhoeven 2024-02-26 14:01 ` Lad, Prabhakar 2024-02-26 14:01 ` Lad, Prabhakar 2024-02-19 16:09 ` [PATCH 4/4] arm64: defconfig: Enable R9A09G057 SoC Prabhakar 2024-02-19 16:09 ` Prabhakar 2024-02-26 13:43 ` Geert Uytterhoeven 2024-02-26 13:43 ` Geert Uytterhoeven
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