From: Bin Meng <bmeng.cn@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation
Date: Fri, 6 Aug 2021 10:26:39 +0800 [thread overview]
Message-ID: <CAEUhbmWZxOnOoJ0E33PjQwm_VV6wnZPaB=Z9scGk5ghbA=oZyg@mail.gmail.com> (raw)
In-Reply-To: <20210724122407.2486558-4-anup.patel@wdc.com>
On Sat, Jul 24, 2021 at 8:24 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We re-factor and break the FDT generation into smaller functions
> so that it is easier to modify FDT generation for different
> configurations of virt machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> hw/riscv/virt.c | 521 ++++++++++++++++++++++++++++++------------------
> 1 file changed, 324 insertions(+), 197 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Atish Patra <atish.patra@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation
Date: Fri, 6 Aug 2021 10:26:39 +0800 [thread overview]
Message-ID: <CAEUhbmWZxOnOoJ0E33PjQwm_VV6wnZPaB=Z9scGk5ghbA=oZyg@mail.gmail.com> (raw)
In-Reply-To: <20210724122407.2486558-4-anup.patel@wdc.com>
On Sat, Jul 24, 2021 at 8:24 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We re-factor and break the FDT generation into smaller functions
> so that it is easier to modify FDT generation for different
> configurations of virt machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> hw/riscv/virt.c | 521 ++++++++++++++++++++++++++++++------------------
> 1 file changed, 324 insertions(+), 197 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
next prev parent reply other threads:[~2021-08-06 2:27 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-24 12:24 [PATCH v2 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-07-24 12:24 ` [PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-04 0:59 ` Alistair Francis
2021-08-04 0:59 ` Alistair Francis
2021-08-06 1:34 ` Bin Meng
2021-08-06 1:34 ` Bin Meng
2021-07-24 12:24 ` [PATCH v2 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-06 2:25 ` Bin Meng
2021-08-06 2:25 ` Bin Meng
2021-08-27 10:08 ` Anup Patel
2021-08-27 10:08 ` Anup Patel
2021-07-24 12:24 ` [PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-05 6:08 ` Alistair Francis
2021-08-05 6:08 ` Alistair Francis
2021-08-06 2:26 ` Bin Meng [this message]
2021-08-06 2:26 ` Bin Meng
2021-07-24 12:24 ` [PATCH v2 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-05 6:09 ` Alistair Francis
2021-08-05 6:09 ` Alistair Francis
2021-08-05 6:12 ` Alistair Francis
2021-08-05 6:12 ` Alistair Francis
2021-08-06 2:30 ` Bin Meng
2021-08-06 2:30 ` Bin Meng
2021-08-27 10:29 ` Anup Patel
2021-08-27 10:29 ` Anup Patel
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